{"id":"https://openalex.org/W2549918039","doi":"https://doi.org/10.1109/isicir.2014.7029467","title":"Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control","display_name":"Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2549918039","doi":"https://doi.org/10.1109/isicir.2014.7029467","mag":"2549918039"},"language":"en","primary_location":{"id":"doi:10.1109/isicir.2014.7029467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100327662","display_name":"Young\u2010Hoon Kim","orcid":"https://orcid.org/0000-0003-1810-6885"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Younghoon Kim","raw_affiliation_strings":["Dept. Electronic Eng., Hanyang University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. Electronic Eng., Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038544613","display_name":"Min\u2010Ki Jeon","orcid":null},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Min-Ki Jeon","raw_affiliation_strings":["Dept. Electronic Eng., Hanyang University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. Electronic Eng., Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091297210","display_name":"Changsik Yoo","orcid":"https://orcid.org/0000-0001-7945-5400"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Changsik Yoo","raw_affiliation_strings":["Dept. Electronic Eng., Hanyang University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. Electronic Eng., Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100327662"],"corresponding_institution_ids":["https://openalex.org/I4575257"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.27394575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"82"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.9198518991470337},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9194660186767578},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8253207206726074},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.8091790676116943},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.6708793640136719},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5564892292022705},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.5166671276092529},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44222527742385864},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.44072264432907104},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.42584142088890076},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4150940179824829},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39174357056617737},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.38445842266082764},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3152499496936798},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21149379014968872},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.17019864916801453},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07088837027549744},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06679058074951172}],"concepts":[{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.9198518991470337},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9194660186767578},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8253207206726074},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.8091790676116943},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.6708793640136719},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5564892292022705},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.5166671276092529},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44222527742385864},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.44072264432907104},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.42584142088890076},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4150940179824829},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39174357056617737},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.38445842266082764},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3152499496936798},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21149379014968872},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.17019864916801453},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07088837027549744},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06679058074951172},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isicir.2014.7029467","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2030871918","https://openalex.org/W2055913428","https://openalex.org/W2062952706","https://openalex.org/W2067333289","https://openalex.org/W2105386586","https://openalex.org/W2112008043","https://openalex.org/W2117325338","https://openalex.org/W2137120286","https://openalex.org/W2145712943","https://openalex.org/W2150783292","https://openalex.org/W2151100180","https://openalex.org/W2151494083","https://openalex.org/W2163630970","https://openalex.org/W2166268103","https://openalex.org/W6658145082","https://openalex.org/W6664561192"],"related_works":["https://openalex.org/W1488060887","https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W1994021281","https://openalex.org/W2043945969","https://openalex.org/W2103754166","https://openalex.org/W2139484866","https://openalex.org/W2058003010","https://openalex.org/W1994059163"],"abstract_inverted_index":{"A":[0],"digital":[1],"phase":[2,12,19,30],"locked":[3],"loop":[4],"(DPLL)":[5],"has":[6,72,98],"been":[7,73],"developed":[8],"in":[9,75],"which":[10],"the":[11,24,27,42,47,50,58,61,68,92,96,102,106],"detection":[13,31],"is":[14],"performed":[15],"by":[16],"a":[17,76],"bangbang":[18],"detector":[20],"(BBPD).":[21],"By":[22],"dithering":[23,94],"offset":[25,69,93],"of":[26,41,49,57,60,95,105],"BBPD,":[28],"its":[29],"gain":[32],"can":[33,52],"be":[34,37,53],"made":[35],"to":[36],"constant":[38,55],"and":[39,80],"independent":[40],"reference":[43,62],"clock":[44,63],"jitter.":[45,64],"Therefore":[46],"bandwidth":[48],"DPLL":[51,66,107],"kept":[54],"regardless":[56],"magnitude":[59],"The":[65,88],"with":[67],"dithered":[70],"BBPD":[71,97],"implemented":[74],"65-nm":[77],"CMOS":[78],"process":[79],"occupies":[81],"only":[82],"0.098-mm":[83],"<sup":[84],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[85],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[86],".":[87],"measurement":[89],"results":[90],"show":[91],"negligible":[99],"effect":[100],"on":[101],"period":[103],"jitter":[104],"output":[108],"clock.":[109]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-05-12T08:28:47.272897","created_date":"2025-10-10T00:00:00"}