{"id":"https://openalex.org/W2041541785","doi":"https://doi.org/10.1109/isicir.2014.7029458","title":"Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS","display_name":"Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2041541785","doi":"https://doi.org/10.1109/isicir.2014.7029458","mag":"2041541785"},"language":"en","primary_location":{"id":"doi:10.1109/isicir.2014.7029458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029458","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108046742","display_name":"Yuejun Zhang","orcid":"https://orcid.org/0000-0003-1132-6332"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yuejun Zhang","raw_affiliation_strings":["Institude of Circuits and Systems, Ningbo University, Ningbo, China","Institude of Circuits and Systems, Ningbo University Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106892182","display_name":"Pengjun Wang","orcid":"https://orcid.org/0000-0002-1461-3719"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pengjun Wang","raw_affiliation_strings":["Institude of Circuits and Systems, Ningbo University, Ningbo, China","Institude of Circuits and Systems, Ningbo University Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101752014","display_name":"Jianrui Li","orcid":"https://orcid.org/0000-0003-4548-8102"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianrui Li","raw_affiliation_strings":["Institude of Circuits and Systems, Ningbo University, Ningbo, China","Institude of Circuits and Systems, Ningbo University Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100438679","display_name":"Gang Li","orcid":"https://orcid.org/0000-0002-2463-8426"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gang Li","raw_affiliation_strings":["Institude of Circuits and Systems, Ningbo University, Ningbo, China","Institude of Circuits and Systems, Ningbo University Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Institude of Circuits and Systems, Ningbo University Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108046742"],"corresponding_institution_ids":["https://openalex.org/I109935558"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1046656,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"41","issue":null,"first_page":"324","last_page":"327"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9753999710083008,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.8339104652404785},{"id":"https://openalex.org/keywords/physical-unclonable-function","display_name":"Physical unclonable function","score":0.8337286114692688},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6338682770729065},{"id":"https://openalex.org/keywords/randomness","display_name":"Randomness","score":0.5760809183120728},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.542984664440155},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5184821486473083},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49918341636657715},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4176042973995209},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3175199031829834},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.26273301243782043},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24520468711853027},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2262696623802185},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0687379240989685}],"concepts":[{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.8339104652404785},{"id":"https://openalex.org/C8643368","wikidata":"https://www.wikidata.org/wiki/Q4046262","display_name":"Physical unclonable function","level":3,"score":0.8337286114692688},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6338682770729065},{"id":"https://openalex.org/C125112378","wikidata":"https://www.wikidata.org/wiki/Q176640","display_name":"Randomness","level":2,"score":0.5760809183120728},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.542984664440155},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5184821486473083},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49918341636657715},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4176042973995209},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3175199031829834},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.26273301243782043},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24520468711853027},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2262696623802185},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0687379240989685},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isicir.2014.7029458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029458","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1971935236","https://openalex.org/W2001067488","https://openalex.org/W2003423506","https://openalex.org/W2030905055","https://openalex.org/W2041435997","https://openalex.org/W2044389004","https://openalex.org/W2047055294","https://openalex.org/W2051441441","https://openalex.org/W2062805023","https://openalex.org/W2067713489","https://openalex.org/W2123482651","https://openalex.org/W2138874069","https://openalex.org/W2169212403","https://openalex.org/W4237236484"],"related_works":["https://openalex.org/W4386278306","https://openalex.org/W4375857400","https://openalex.org/W4288102672","https://openalex.org/W4386215421","https://openalex.org/W2789961440","https://openalex.org/W2793303626","https://openalex.org/W2582407527","https://openalex.org/W4392606204","https://openalex.org/W2905275340","https://openalex.org/W3043307929"],"abstract_inverted_index":{"Physical":[0],"Unclonable":[1],"Functions":[2],"(PUFs)":[3],"exploits":[4],"static":[5],"process":[6],"variation":[7],"across":[8],"integrated":[9],"circuits":[10,64],"in":[11,35],"the":[12,42,50,73,84],"manufacturing":[13],"processes":[14],"to":[15,67],"generate":[16],"many":[17],"unique,":[18],"random":[19],"and":[20,44,62],"unclonable":[21],"security":[22],"keys.":[23],"In":[24,70],"this":[25],"paper,":[26],"a":[27,90],"threshold":[28,57],"dominant":[29,46,58],"delay":[30,59],"PUFs":[31],"(TDD-PUFs)":[32],"is":[33,86],"designed":[34],"TSMC":[36],"65nm":[37],"CMOS":[38],"technology.":[39],"After":[40],"configuring":[41],"nMOSFET":[43],"pMOSFET":[45],"delay,":[47],"TDD-PUFs":[48,77],"updates":[49],"key":[51],"without":[52],"physically":[53],"replace.":[54],"N":[55],"stages":[56],"cell,":[60],"arbiter":[61],"other":[63],"are":[65],"organized":[66],"realize":[68],"TDD-PUFs.":[69],"custom":[71],"designed,":[72],"layout":[74],"of":[75,92],"128-bit":[76],"occupies":[78],"358.62\u03bcm\u00d7154.65\u03bcm.":[79],"Experimental":[80],"results":[81],"show":[82],"that":[83],"randomness":[85],"about":[87],"100%":[88],"over":[89],"range":[91],"environmental":[93],"variations.":[94]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}