{"id":"https://openalex.org/W2793007427","doi":"https://doi.org/10.1109/ised.2017.8303950","title":"Cost effective realization of XOR logic in QCA","display_name":"Cost effective realization of XOR logic in QCA","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2793007427","doi":"https://doi.org/10.1109/ised.2017.8303950","mag":"2793007427"},"language":"en","primary_location":{"id":"doi:10.1109/ised.2017.8303950","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303950","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021521188","display_name":"Mrinal Goswami","orcid":"https://orcid.org/0000-0001-5856-6830"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mrinal Goswami","raw_affiliation_strings":["Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057002772","display_name":"Kumar Mohit","orcid":null},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kumar Mohit","raw_affiliation_strings":["Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044215390","display_name":"Bibhash Sen","orcid":"https://orcid.org/0000-0003-4803-3074"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bibhash Sen","raw_affiliation_strings":["Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Nationa Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021521188"],"corresponding_institution_ids":["https://openalex.org/I155837530"],"apc_list":null,"apc_paid":null,"fwci":1.1356,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.81306648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10382","display_name":"Quantum and electron transport phenomena","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.8180395364761353},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6592256426811218},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6218710541725159},{"id":"https://openalex.org/keywords/quantum-dot-cellular-automaton","display_name":"Quantum dot cellular automaton","score":0.5944544672966003},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.593389093875885},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5833799839019775},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5564482808113098},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5051489472389221},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.503736674785614},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3498929738998413},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2421533167362213},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21146121621131897},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.1870308816432953},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1766209900379181}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.8180395364761353},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6592256426811218},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6218710541725159},{"id":"https://openalex.org/C116523029","wikidata":"https://www.wikidata.org/wiki/Q7269040","display_name":"Quantum dot cellular automaton","level":3,"score":0.5944544672966003},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.593389093875885},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5833799839019775},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5564482808113098},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5051489472389221},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.503736674785614},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3498929738998413},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2421533167362213},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21146121621131897},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.1870308816432953},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1766209900379181}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ised.2017.8303950","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303950","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1760221819","https://openalex.org/W1963557219","https://openalex.org/W1976924286","https://openalex.org/W1995209593","https://openalex.org/W1999347979","https://openalex.org/W2009424868","https://openalex.org/W2027703730","https://openalex.org/W2029091937","https://openalex.org/W2059030116","https://openalex.org/W2077978408","https://openalex.org/W2098416075","https://openalex.org/W2133403974","https://openalex.org/W2137793259","https://openalex.org/W2275057897","https://openalex.org/W2563749369","https://openalex.org/W2735701322","https://openalex.org/W6680700465"],"related_works":["https://openalex.org/W2140092109","https://openalex.org/W2119985366","https://openalex.org/W2317514856","https://openalex.org/W2785627314","https://openalex.org/W4246304997","https://openalex.org/W2994667198","https://openalex.org/W3213263904","https://openalex.org/W1966410745","https://openalex.org/W2536833528","https://openalex.org/W2530808634"],"abstract_inverted_index":{"Quantum-dot":[0],"cellular":[1],"automata":[2],"(QCA)":[3],"has":[4,30,49,87],"emerged":[5],"as":[6,116,118],"a":[7,52,59,65,83],"promising":[8],"and":[9,70,100,121,141],"efficient":[10,40,96,113],"nanoscale":[11,45],"technology":[12],"overcoming":[13],"the":[14,17,21,25,36,44,55,62,73,76,105,108,146],"demerits":[15],"of":[16,27,38,64,107,137],"CMOS":[18],"technology.":[19],"With":[20],"rapid":[22],"development":[23],"in":[24,35,43,135,143],"field":[26],"nanotechnology,":[28],"there":[29],"been":[31,51,88,129],"an":[32,95,112,119,122],"exponential":[33],"increase":[34],"practice":[37],"designing":[39],"logic":[41],"circuits":[42],"era.":[46],"However,":[47],"it":[48],"always":[50],"challenge":[53],"for":[54],"designers":[56],"to":[57,75,93,145],"design":[58],"circuit":[60],"meeting":[61],"requirements":[63],"fast":[66],"signal":[67],"transfer":[68],"mechanism":[69],"hence":[71],"minimizing":[72],"delay":[74],"lowest":[77],"possible":[78],"value.":[79],"In":[80],"this":[81],"paper,":[82],"5-input":[84],"majority":[85],"voter":[86],"proposed":[89,109,149],"which":[90,131],"is":[91],"used":[92],"synthesize":[94],"3-input":[97],"XOR":[98,110],"gate":[99],"XNOR":[101],"gate.":[102],"To":[103],"find":[104],"significance":[106],"gate,":[111],"full":[114],"adder":[115],"well":[117],"odd":[120],"even":[123],"bit":[124],"parity":[125],"generator":[126],"have":[127],"also":[128],"implemented":[130],"shows":[132],"significant":[133],"improvement":[134],"terms":[136],"area,":[138],"cell":[139],"count":[140],"latency":[142],"comparison":[144],"other":[147],"previously":[148],"circuits.":[150]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
