{"id":"https://openalex.org/W2793507437","doi":"https://doi.org/10.1109/ised.2017.8303930","title":"A placement optimization technique for 3D IC","display_name":"A placement optimization technique for 3D IC","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2793507437","doi":"https://doi.org/10.1109/ised.2017.8303930","mag":"2793507437"},"language":"en","primary_location":{"id":"doi:10.1109/ised.2017.8303930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039922629","display_name":"Sabyasachee Banerjee","orcid":"https://orcid.org/0000-0001-8934-0391"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Sabyasachee Banerjee","raw_affiliation_strings":["Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033411778","display_name":"Subhashis Majumder","orcid":"https://orcid.org/0000-0002-0849-9016"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Subhashis Majumder","raw_affiliation_strings":["Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004640128","display_name":"Abhishek Varma","orcid":"https://orcid.org/0000-0002-0773-2859"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Abhishek Varma","raw_affiliation_strings":["Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Heritage Institute of Technology, Kolkata, West Bengal","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059700720","display_name":"Debesh K. Das","orcid":"https://orcid.org/0000-0003-1736-1497"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Debesh K. Das","raw_affiliation_strings":["Department of Computer Science and Engineering, Jadavpur University, Kolkata, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Jadavpur University, Kolkata, India","institution_ids":["https://openalex.org/I170979836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5039922629"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.54865593,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.6513468027114868},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6178094744682312},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5930995941162109},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.4655298590660095},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45759114623069763},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4553535282611847},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4428308606147766},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4427240192890167},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4387549161911011},{"id":"https://openalex.org/keywords/connection","display_name":"Connection (principal bundle)","score":0.4106261134147644},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.3926340341567993},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3624998927116394},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3595345616340637},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2435591220855713},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24193143844604492},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.22352832555770874},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18437767028808594},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11678162217140198}],"concepts":[{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.6513468027114868},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6178094744682312},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5930995941162109},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.4655298590660095},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45759114623069763},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4553535282611847},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4428308606147766},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4427240192890167},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4387549161911011},{"id":"https://openalex.org/C13355873","wikidata":"https://www.wikidata.org/wiki/Q2920850","display_name":"Connection (principal bundle)","level":2,"score":0.4106261134147644},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3926340341567993},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3624998927116394},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3595345616340637},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2435591220855713},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24193143844604492},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.22352832555770874},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18437767028808594},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11678162217140198},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ised.2017.8303930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1977384983","https://openalex.org/W2007901850","https://openalex.org/W2052075409","https://openalex.org/W2114853176","https://openalex.org/W2152965341","https://openalex.org/W2162877164","https://openalex.org/W2555661487","https://openalex.org/W4248596413","https://openalex.org/W6684332989"],"related_works":["https://openalex.org/W2156550631","https://openalex.org/W2155675690","https://openalex.org/W2005457717","https://openalex.org/W1563562883","https://openalex.org/W2185927297","https://openalex.org/W4389383710","https://openalex.org/W2036121598","https://openalex.org/W2111591643","https://openalex.org/W4245549415","https://openalex.org/W2163932442"],"abstract_inverted_index":{"This":[0],"paper":[1,44],"presents":[2],"a":[3,31,53,66],"placement":[4],"algorithm":[5,40],"for":[6],"designing":[7],"3D":[8,28],"Integrated":[9],"Circuits":[10],"(ICs).":[11],"Typical":[12],"2D":[13],"ICs":[14],"are":[15,24],"unable":[16],"to":[17,49,84],"provide":[18],"the":[19,61,69,76,79,86,97],"high":[20],"connection":[21],"speeds":[22],"that":[23,46],"offered":[25],"by":[26],"its":[27],"variants":[29],"at":[30],"lower":[32],"cost,":[33],"consuming":[34],"less":[35],"power":[36],"and":[37],"space.":[38],"The":[39],"proposed":[41],"in":[42,52,60,68,73],"this":[43],"demonstrates":[45],"assigning":[47],"blocks":[48],"each":[50],"layer":[51],"compact":[54],"fashion":[55],"can":[56],"achieve":[57],"substantial":[58],"savings":[59],"total":[62,87],"wirelength":[63],"along":[64],"with":[65],"reduction":[67],"number":[70,92],"of":[71,75,93],"TSVs":[72],"most":[74],"cases.":[77],"On":[78],"whole,":[80],"our":[81],"method":[82],"helps":[83],"reduce":[85],"wirelength,":[88],"as":[89,91],"well":[90],"TSVs,":[94],"while":[95],"satisfying":[96],"area-constraints.":[98]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
