{"id":"https://openalex.org/W2790231606","doi":"https://doi.org/10.1109/ised.2017.8303926","title":"Single cycle RISC-V micro architecture processor and its FPGA prototype","display_name":"Single cycle RISC-V micro architecture processor and its FPGA prototype","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2790231606","doi":"https://doi.org/10.1109/ised.2017.8303926","mag":"2790231606"},"language":"en","primary_location":{"id":"doi:10.1109/ised.2017.8303926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003148257","display_name":"Don Kurian Dennis","orcid":null},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Don Kurian Dennis","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028325459","display_name":"Ayushi Priyam","orcid":"https://orcid.org/0000-0001-5432-8392"},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ayushi Priyam","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028662547","display_name":"Sukhpreet Singh Virk","orcid":null},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sukhpreet Singh Virk","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103910438","display_name":"Sajal Agrawal","orcid":null},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sajal Agrawal","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020888417","display_name":"Tanuj Sharma","orcid":"https://orcid.org/0000-0003-0054-6153"},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tanuj Sharma","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101597015","display_name":"Arijit Mondal","orcid":"https://orcid.org/0000-0001-5060-1427"},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Arijit Mondal","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015170706","display_name":"Kailash Chandra Ray","orcid":"https://orcid.org/0000-0002-7345-1377"},"institutions":[{"id":"https://openalex.org/I132153292","display_name":"Indian Institute of Technology Patna","ror":"https://ror.org/01ft5vz71","country_code":"IN","type":"education","lineage":["https://openalex.org/I132153292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kailash Chandra Ray","raw_affiliation_strings":["Indian Institute of Technology, Patna"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Patna","institution_ids":["https://openalex.org/I132153292"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5003148257"],"corresponding_institution_ids":["https://openalex.org/I132153292"],"apc_list":null,"apc_paid":null,"fwci":2.9291,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":{"value":0.9298726,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.8231677412986755},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7630898952484131},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7409794330596924},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6617608666419983},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6114087104797363},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.4195362329483032},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41029611229896545},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3389796018600464},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.33816230297088623}],"concepts":[{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.8231677412986755},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7630898952484131},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7409794330596924},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6617608666419983},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6114087104797363},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.4195362329483032},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41029611229896545},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3389796018600464},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.33816230297088623}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ised.2017.8303926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2017.8303926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W576364895","https://openalex.org/W1505284028","https://openalex.org/W1559327029","https://openalex.org/W2187802606","https://openalex.org/W2231924698","https://openalex.org/W6690000262"],"related_works":["https://openalex.org/W2062172248","https://openalex.org/W2128502296","https://openalex.org/W4364295250","https://openalex.org/W2088017777","https://openalex.org/W3167587462","https://openalex.org/W3033918533","https://openalex.org/W2806352516","https://openalex.org/W2789901355","https://openalex.org/W1480407846","https://openalex.org/W3027367487"],"abstract_inverted_index":{"In":[0],"this":[1,45],"paper,":[2],"development":[3,30],"of":[4],"a":[5,51],"fully":[6],"synthesizable":[7],"32-bit":[8],"processor":[9,20,49,58,65],"based":[10],"on":[11,74],"the":[12,84],"open-source":[13],"RISC-V":[14,29,57],"(RV32I)":[15],"ISA":[16],"is":[17,21,41,50,66,81,88,92],"presented.":[18],"This":[19,80],"designed":[22],"for":[23],"targeting":[24],"low-cost":[25],"embedded":[26],"devices.":[27],"A":[28],"and":[31,37,71],"validation":[32],"framework":[33],"with":[34,59],"assembling":[35],"tools":[36],"automated":[38],"test":[39],"suits":[40],"also":[42],"presented":[43],"in":[44,68],"paper.":[46],"The":[47,63,90],"resulting":[48],"single":[52],"core,":[53],"in-order,":[54],"non-bus":[55],"based,":[56],"low":[60],"hardware":[61],"complexity.":[62],"proposed":[64],"implemented":[67],"Verilog":[69],"HDL":[70],"further":[72],"prototyped":[73],"FPGA":[75],"\"Spartan":[76],"3E":[77],"XC3S500E\"":[78],"board.":[79],"found":[82],"that":[83],"maximum":[85],"operating":[86],"frequency":[87],"32MHz.":[89],"power":[91],"estimated":[93],"to":[94],"be":[95],"7.9mW":[96],"using":[97],"Xilinx":[98],"Power":[99],"Analyzer.":[100]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":8},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
