{"id":"https://openalex.org/W2736291601","doi":"https://doi.org/10.1109/ised.2016.7977092","title":"CA based protocol processor for heterogeneous CMPs","display_name":"CA based protocol processor for heterogeneous CMPs","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2736291601","doi":"https://doi.org/10.1109/ised.2016.7977092","mag":"2736291601"},"language":"en","primary_location":{"id":"doi:10.1109/ised.2016.7977092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2016.7977092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Sixth International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004502943","display_name":"Bidesh Chakraborty","orcid":"https://orcid.org/0000-0002-7280-8995"},"institutions":[{"id":"https://openalex.org/I175399479","display_name":"Haldia Institute of Technology","ror":"https://ror.org/0211bs523","country_code":"IN","type":"education","lineage":["https://openalex.org/I175399479"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bidesh Chakraborty","raw_affiliation_strings":["Computer Science & Engineering HIT, Haldia, WB, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering HIT, Haldia, WB, India","institution_ids":["https://openalex.org/I175399479"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024913744","display_name":"Mamata Dalui","orcid":"https://orcid.org/0000-0001-5829-541X"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mamata Dalui","raw_affiliation_strings":["Computer Science & Engineering NIT, Durgapur, WB, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering NIT, Durgapur, WB, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089134920","display_name":"Biplab K. Sikdar","orcid":"https://orcid.org/0000-0002-9394-8540"},"institutions":[{"id":"https://openalex.org/I98365261","display_name":"Indian Institute of Engineering Science and Technology, Shibpur","ror":"https://ror.org/02ytfzr55","country_code":"IN","type":"education","lineage":["https://openalex.org/I98365261"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Biplab K. Sikdar","raw_affiliation_strings":["Computer Science & Technology IIEST, Shibpur, WB, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Technology IIEST, Shibpur, WB, India","institution_ids":["https://openalex.org/I98365261"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.26997714,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"254","last_page":"258"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.836845874786377},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6504644155502319},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.6490166187286377},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5795068740844727},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5639697313308716},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.556082010269165},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.554867148399353},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5392282605171204},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.5238485336303711},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44502145051956177},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4289107024669647},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4279826283454895},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3675551414489746},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.29037997126579285},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17081254720687866},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.1438407301902771}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.836845874786377},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6504644155502319},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.6490166187286377},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5795068740844727},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5639697313308716},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.556082010269165},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.554867148399353},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5392282605171204},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.5238485336303711},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44502145051956177},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4289107024669647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4279826283454895},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3675551414489746},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.29037997126579285},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17081254720687866},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.1438407301902771},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ised.2016.7977092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ised.2016.7977092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 Sixth International Symposium on Embedded Computing and System Design (ISED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W29127030","https://openalex.org/W1511688816","https://openalex.org/W1580368359","https://openalex.org/W1978125087","https://openalex.org/W2111422492","https://openalex.org/W2153184575"],"related_works":["https://openalex.org/W4230687177","https://openalex.org/W1968829728","https://openalex.org/W2349859869","https://openalex.org/W2051365847","https://openalex.org/W1539379314","https://openalex.org/W2367249529","https://openalex.org/W3120118008","https://openalex.org/W4214765864","https://openalex.org/W1943342825","https://openalex.org/W2408839732"],"abstract_inverted_index":{"In":[0],"this":[1],"work":[2],"we":[3,41],"propose":[4],"a":[5,18,23,78,93],"design":[6,64],"approach":[7],"for":[8],"the":[9,15,38,43,63,75],"Protocol":[10],"Processor":[11],"(PP)":[12],"to":[13],"determine":[14],"state":[16],"of":[17,60,77,99],"data":[19,79],"block":[20,80],"accurately":[21],"in":[22,53],"heterogeneous":[24],"Chip":[25],"Multiprocessors":[26],"(CMPs)":[27],"where":[28],"different":[29],"cores":[30],"may":[31],"follow":[32],"separate":[33],"cache":[34],"coherence":[35],"protocols.":[36],"For":[37],"proposed":[39],"design,":[40],"consider":[42],"cellular":[44],"automata":[45],"(CA)":[46],"modelling":[47],"tool":[48],"invented":[49],"by":[50,91],"von":[51],"Neumann":[52],"1950s.":[54],"The":[55,69],"structural":[56],"regularity":[57],"and":[58,67,89],"modularity":[59],"CA":[61,70],"makes":[62],"highly":[65],"scalable":[66],"robust.":[68],"based":[71],"PP":[72,96],"while":[73],"computing":[74],"states":[76],"on":[81],"read/write":[82],"operation,":[83],"can":[84],"capture":[85],"defects,":[86],"if":[87],"any,":[88],"there":[90],"realizes":[92],"fault":[94],"tolerant":[95],"without":[97],"introduction":[98],"additional":[100],"hardware":[101],"logic.":[102]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}