{"id":"https://openalex.org/W2991342931","doi":"https://doi.org/10.1109/iscit.2019.8905155","title":"Technology Education Challenges and Solution to Design a Process Design Kit for Digital CMOS Technology in Vietnam","display_name":"Technology Education Challenges and Solution to Design a Process Design Kit for Digital CMOS Technology in Vietnam","publication_year":2019,"publication_date":"2019-09-01","ids":{"openalex":"https://openalex.org/W2991342931","doi":"https://doi.org/10.1109/iscit.2019.8905155","mag":"2991342931"},"language":"en","primary_location":{"id":"doi:10.1109/iscit.2019.8905155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2019.8905155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 19th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074680541","display_name":"Cong Thinh Dang","orcid":null},"institutions":[{"id":"https://openalex.org/I47265099","display_name":"Ho Chi Minh City University of Technology","ror":"https://ror.org/04qva2324","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023","https://openalex.org/I47265099"]},{"id":"https://openalex.org/I123565023","display_name":"Vietnam National University Ho Chi Minh City","ror":"https://ror.org/00waaqh38","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023"]}],"countries":["VN"],"is_corresponding":true,"raw_author_name":"Cong THINH Dang","raw_affiliation_strings":["Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam"],"affiliations":[{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","institution_ids":["https://openalex.org/I47265099"]},{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam","institution_ids":["https://openalex.org/I47265099","https://openalex.org/I123565023"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079169471","display_name":"Thanh TOI Le","orcid":null},"institutions":[{"id":"https://openalex.org/I123565023","display_name":"Vietnam National University Ho Chi Minh City","ror":"https://ror.org/00waaqh38","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023"]},{"id":"https://openalex.org/I47265099","display_name":"Ho Chi Minh City University of Technology","ror":"https://ror.org/04qva2324","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023","https://openalex.org/I47265099"]}],"countries":["VN"],"is_corresponding":false,"raw_author_name":"Thanh TOI Le","raw_affiliation_strings":["Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam"],"affiliations":[{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","institution_ids":["https://openalex.org/I47265099"]},{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam","institution_ids":["https://openalex.org/I47265099","https://openalex.org/I123565023"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045777504","display_name":"Trang Hoang","orcid":"https://orcid.org/0000-0001-7317-9708"},"institutions":[{"id":"https://openalex.org/I47265099","display_name":"Ho Chi Minh City University of Technology","ror":"https://ror.org/04qva2324","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023","https://openalex.org/I47265099"]},{"id":"https://openalex.org/I123565023","display_name":"Vietnam National University Ho Chi Minh City","ror":"https://ror.org/00waaqh38","country_code":"VN","type":"education","lineage":["https://openalex.org/I123565023"]}],"countries":["VN"],"is_corresponding":false,"raw_author_name":"Hoang TRANG","raw_affiliation_strings":["Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam"],"affiliations":[{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM,Ho Chi Minh City,Vietnam","institution_ids":["https://openalex.org/I47265099"]},{"raw_affiliation_string":"Ho Chi Minh City University of Technology-VNU HCM, Ho Chi Minh City, Vietnam","institution_ids":["https://openalex.org/I47265099","https://openalex.org/I123565023"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5074680541"],"corresponding_institution_ids":["https://openalex.org/I123565023","https://openalex.org/I47265099"],"apc_list":null,"apc_paid":null,"fwci":0.1192,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48457532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"381","last_page":"385"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7680432796478271},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7578617334365845},{"id":"https://openalex.org/keywords/design-technology","display_name":"Design technology","score":0.5919128656387329},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5819593667984009},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5579149127006531},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5374423265457153},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5137408971786499},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5064343214035034},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.46555855870246887},{"id":"https://openalex.org/keywords/design-process","display_name":"Design process","score":0.45730429887771606},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4561464488506317},{"id":"https://openalex.org/keywords/engineering-design-process","display_name":"Engineering design process","score":0.4466620683670044},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4323529005050659},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.42723825573921204},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.38083022832870483},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32741308212280273},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29525473713874817},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.2944481372833252},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28542953729629517},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27705618739128113},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.276489794254303},{"id":"https://openalex.org/keywords/work-in-process","display_name":"Work in process","score":0.1575717329978943}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7680432796478271},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7578617334365845},{"id":"https://openalex.org/C179737136","wikidata":"https://www.wikidata.org/wiki/Q5264382","display_name":"Design technology","level":2,"score":0.5919128656387329},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5819593667984009},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5579149127006531},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5374423265457153},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5137408971786499},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5064343214035034},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.46555855870246887},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.45730429887771606},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4561464488506317},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.4466620683670044},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4323529005050659},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.42723825573921204},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.38083022832870483},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32741308212280273},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29525473713874817},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2944481372833252},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28542953729629517},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27705618739128113},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.276489794254303},{"id":"https://openalex.org/C174998907","wikidata":"https://www.wikidata.org/wiki/Q357662","display_name":"Work in process","level":2,"score":0.1575717329978943},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscit.2019.8905155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2019.8905155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 19th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2009353040","https://openalex.org/W2024277841","https://openalex.org/W2059812140","https://openalex.org/W2076654948","https://openalex.org/W2139002947","https://openalex.org/W2282229428","https://openalex.org/W2288423105","https://openalex.org/W2294559665","https://openalex.org/W2533354906","https://openalex.org/W2542226650","https://openalex.org/W2564024795","https://openalex.org/W4244015912","https://openalex.org/W6729110917","https://openalex.org/W6729161521","https://openalex.org/W6825983753"],"related_works":["https://openalex.org/W2171793444","https://openalex.org/W2743305891","https://openalex.org/W3205162826","https://openalex.org/W1965232212","https://openalex.org/W2151657833","https://openalex.org/W4321510758","https://openalex.org/W2070693700","https://openalex.org/W1596716095","https://openalex.org/W2991342931","https://openalex.org/W2056740847"],"abstract_inverted_index":{"In":[0,41,141],"the":[1,4,14,32,88,123,144],"electronic":[2],"field,":[3],"complexity":[5],"of":[6,63,116,167],"Integrated":[7],"Circuits":[8],"design":[9,16,34,57,74,90,146,149,177],"continues":[10],"to":[11,54,73],"increase.":[12],"Therefore,":[13],"full-custom":[15],"is":[17,35,51,85,125],"not":[18],"feasible":[19],"in":[20,31,44,58,87,93,98,100],"most":[21],"cases":[22],"and":[23,91,95,109,122,150,171,178],"replaced":[24],"by":[25],"semi-custom":[26,33,56,89],"design.":[27],"The":[28],"main":[29],"component":[30],"Process":[36,76],"Design":[37,77],"Kit":[38,78],"(PDK)":[39],"digital.":[40],"developing":[42],"countries":[43],"Southeast":[45],"Asia":[46],"such":[47],"as":[48,132,134],"Vietnam,":[49],"it":[50],"a":[52,75,164],"challenge":[53],"approach":[55],"education":[59,97],"at":[60],"university":[61,99],"because":[62],"PDK":[64],"digital's":[65],"cost":[66],"or":[67],"license.":[68],"This":[69,102],"paper":[70],"discusses":[71],"how":[72],"digital":[79],"for":[80,152,176],"CMOS":[81,161],"180nm":[82,160],"technology":[83,162],"which":[84],"used":[86,175],"applied":[92],"undergraduate":[94],"graduate":[96],"Vietnam.":[101],"work":[103],"includes":[104],"Standard":[105],"Cell":[106],"Library":[107],"(SCL)":[108],"Wire-Load":[110],"Model":[111],"(WLM).":[112],"A":[113],"complete":[114],"library":[115],"47":[117],"standard":[118],"cells":[119],"are":[120,174],"designed":[121],"methodology":[124,151],"ensured":[126],"through":[127],"schematic":[128],"design,":[129,131],"layout":[130,148],"well":[133],"pin":[135],"capacitance,":[136],"timing,":[137],"power":[138],"dissipation":[139],"models.":[140],"this":[142],"paper,":[143],"SCL":[145],"methodology,":[147],"creating":[153],"characteristics":[154],"have":[155],"been":[156],"developed":[157],"based":[158],"on":[159],"using":[163],"supply":[165],"voltage":[166],"1.8v.":[168],"EDA":[169],"environment":[170],"Ocean":[172],"script":[173],"simulations.":[179]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}