{"id":"https://openalex.org/W2343160172","doi":"https://doi.org/10.1109/iscit.2015.7458373","title":"Clock skew reduction for stacked chips using multiple source buffers","display_name":"Clock skew reduction for stacked chips using multiple source buffers","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2343160172","doi":"https://doi.org/10.1109/iscit.2015.7458373","mag":"2343160172"},"language":"en","primary_location":{"id":"doi:10.1109/iscit.2015.7458373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2015.7458373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 15th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058455305","display_name":"Nanako Niioka","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nanako Niioka","raw_affiliation_strings":["Hirosaki University, Hirosaki-City, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki University, Hirosaki-City, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110646137","display_name":"Masashi Imai","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masashi Imai","raw_affiliation_strings":["Hirosaki University, Hirosaki-City, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki University, Hirosaki-City, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090880748","display_name":"Masa-aki Fukase","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masa-aki Fukase","raw_affiliation_strings":["Hirosaki University, Hirosaki-City, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki University, Hirosaki-City, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053633120","display_name":"Yuuki Miura","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuuki Miura","raw_affiliation_strings":["Hirosaki University, Hirosaki-City, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki University, Hirosaki-City, Japan","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061588831","display_name":"Kaoru Furumi","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kaoru Furumi","raw_affiliation_strings":["Hirosaki Daigaku, Hirosaki, Aomori, JP"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki Daigaku, Hirosaki, Aomori, JP","institution_ids":["https://openalex.org/I146516829"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108528404","display_name":"Atsushi Kurokawa","orcid":null},"institutions":[{"id":"https://openalex.org/I146516829","display_name":"Hirosaki University","ror":"https://ror.org/02syg0q74","country_code":"JP","type":"education","lineage":["https://openalex.org/I146516829"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Kurokawa","raw_affiliation_strings":["Hirosaki University, Hirosaki-City, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hirosaki University, Hirosaki-City, Japan","institution_ids":["https://openalex.org/I146516829"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I146516829"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27475601,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"33","issue":null,"first_page":"327","last_page":"330"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8579171895980835},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7820857167243958},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7815684080123901},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6987090110778809},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.686881422996521},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6481603980064392},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6263641119003296},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6145530343055725},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5514163970947266},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5056924819946289},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5033354163169861},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4915071427822113},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48914578557014465},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.48357313871383667},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4564715325832367},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.427310585975647},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.41140228509902954},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3943478763103485},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.32660022377967834},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2866095304489136},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.26434409618377686},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19534769654273987},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09317338466644287},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08145970106124878}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8579171895980835},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7820857167243958},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7815684080123901},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6987090110778809},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.686881422996521},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6481603980064392},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6263641119003296},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6145530343055725},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5514163970947266},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5056924819946289},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5033354163169861},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4915071427822113},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48914578557014465},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.48357313871383667},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4564715325832367},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.427310585975647},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.41140228509902954},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3943478763103485},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.32660022377967834},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2866095304489136},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.26434409618377686},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19534769654273987},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09317338466644287},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08145970106124878},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscit.2015.7458373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2015.7458373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 15th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1572495393","https://openalex.org/W1964664019","https://openalex.org/W1978639190","https://openalex.org/W1984150960","https://openalex.org/W1987638749","https://openalex.org/W2001560636","https://openalex.org/W2008737256","https://openalex.org/W2013992232","https://openalex.org/W2023256572","https://openalex.org/W2025923707","https://openalex.org/W2025964529","https://openalex.org/W2026950554","https://openalex.org/W2056461583","https://openalex.org/W2077762797","https://openalex.org/W2095080704","https://openalex.org/W2097745015","https://openalex.org/W2100212269","https://openalex.org/W2132333357","https://openalex.org/W2136188627","https://openalex.org/W2158473722","https://openalex.org/W2164217202","https://openalex.org/W4233874110","https://openalex.org/W6656331246"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2144282137","https://openalex.org/W3006003651","https://openalex.org/W2165139624","https://openalex.org/W2127892766"],"abstract_inverted_index":{"In":[0,81],"this":[1,82],"paper,":[2],"we":[3],"propose":[4],"a":[5,15,33,43,105,113],"method":[6,92,115,130],"to":[7,28,78],"reduce":[8,132],"clock":[9,16,34,44,106,119,133],"skew":[10],"among":[11],"stacked":[12],"chips":[13,30,99],"by":[14,111],"distribution":[17],"network":[18],"with":[19,42,52,104],"multiple":[20],"source":[21,107],"buffers":[22],"(MSB":[23],"CDN).":[24],"The":[25,46,70,90,123],"propagation":[26],"delays":[27,85],"all":[29,97],"that":[31,96,127],"need":[32],"signal":[35],"are":[36,64,76,88],"tuned":[37],"only":[38],"in":[39,50,60],"the":[40,53,61,67,74,84,94,98,102,128],"chip":[41,103],"source.":[45],"adjustment":[47],"is":[48],"done":[49],"accordance":[51],"size":[54],"and":[55,86],"number":[56],"of":[57,73],"buffers.":[58],"Receivers":[59],"same":[62],"conditions":[63],"placed":[65],"on":[66],"other":[68],"chips.":[69],"output":[71],"signals":[72],"receivers":[75],"subjected":[77],"waveform":[79],"shaping.":[80],"way,":[83],"slews":[87],"unified.":[89],"proposed":[91,129],"has":[93],"advantage":[95],"except":[100],"for":[101],"can":[108,131],"be":[109],"designed":[110],"using":[112],"conventional":[114],"such":[116],"as":[117],"buffered":[118],"tree":[120],"synthesis":[121],"(CTS).":[122],"experimental":[124],"results":[125],"demonstrate":[126],"skew.":[134]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}