{"id":"https://openalex.org/W2343241460","doi":"https://doi.org/10.1109/iscit.2015.7458341","title":"A wide-range and harmonic-free SAR all-digital delay locked loop","display_name":"A wide-range and harmonic-free SAR all-digital delay locked loop","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2343241460","doi":"https://doi.org/10.1109/iscit.2015.7458341","mag":"2343241460"},"language":"en","primary_location":{"id":"doi:10.1109/iscit.2015.7458341","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2015.7458341","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 15th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114228395","display_name":"Ko\u2010Chi Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ko-Chi Kuo","raw_affiliation_strings":["Dept. Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Dept. Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041624947","display_name":"Sz-Hsien Li","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sz-Hsien Li","raw_affiliation_strings":["Dept. Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Dept. Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5114228395"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.1688223,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"57","issue":null,"first_page":"197","last_page":"200"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8649519681930542},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.73740553855896},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.6409117579460144},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5493943691253662},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.48824623227119446},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.48268890380859375},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4702526330947876},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4627070426940918},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.45981651544570923},{"id":"https://openalex.org/keywords/group-delay-and-phase-delay","display_name":"Group delay and phase delay","score":0.44614356756210327},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.42238783836364746},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3298441767692566},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3217044770717621},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.28063756227493286},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.16188141703605652},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14152371883392334},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13283854722976685},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.124762624502182}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8649519681930542},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.73740553855896},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.6409117579460144},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5493943691253662},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.48824623227119446},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.48268890380859375},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4702526330947876},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4627070426940918},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.45981651544570923},{"id":"https://openalex.org/C123792056","wikidata":"https://www.wikidata.org/wiki/Q365988","display_name":"Group delay and phase delay","level":3,"score":0.44614356756210327},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.42238783836364746},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3298441767692566},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3217044770717621},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.28063756227493286},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.16188141703605652},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14152371883392334},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13283854722976685},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.124762624502182},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscit.2015.7458341","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscit.2015.7458341","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 15th International Symposium on Communications and Information Technologies (ISCIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8500000238418579}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1997079079","https://openalex.org/W2007378435","https://openalex.org/W2043037338","https://openalex.org/W2096748338","https://openalex.org/W2100452539","https://openalex.org/W2106042087","https://openalex.org/W2115350477","https://openalex.org/W2126227985","https://openalex.org/W2144572765","https://openalex.org/W2162720403"],"related_works":["https://openalex.org/W2134109056","https://openalex.org/W2753083610","https://openalex.org/W2171284930","https://openalex.org/W2158959564","https://openalex.org/W2735375340","https://openalex.org/W801590478","https://openalex.org/W2150727772","https://openalex.org/W2561397629","https://openalex.org/W2114352341","https://openalex.org/W3011453599"],"abstract_inverted_index":{"A":[0],"delay":[1,16,30,50,62,99],"locked":[2,63],"loop":[3,64],"(DLL)":[4],"using":[5],"the":[6,14,24,35,40,46,57,73,78,94],"shift-counting":[7],"type":[8],"successive":[9,68],"approximation":[10,69],"register":[11,70],"to":[12,38,55,71,85],"control":[13],"digital":[15],"line":[17,31],"is":[18,32,81,91,101,107,121,136],"proposed.":[19],"It":[20],"mainly":[21],"can":[22],"solve":[23],"problem":[25],"of":[26,42,59],"harmonic":[27],"lock.":[28],"The":[29,88,98,105,119,133],"implemented":[33],"by":[34],"complementary":[36],"way":[37],"improve":[39,56],"range":[41,80],"lockable.":[43],"In":[44,76],"addition,":[45,77],"coarse":[47],"and":[48,113,127,142],"fine":[49],"cell":[51],"are":[52],"also":[53],"utilized":[54],"resolution":[58,100],"delay.":[60],"This":[61],"uses":[65],"a":[66],"10-bit":[67],"achieve":[72],"fast":[74],"locking.":[75],"locking":[79],"from":[82],"100":[83,111,125],"MHz":[84,112,126],"1":[86,117,131,147],"GHz.":[87,118,132,148],"supply":[89],"voltage":[90],"1.2V":[92],"with":[93],"TSMC":[95],"90nm":[96],"process.":[97],"about":[102],"4":[103],"ps.":[104],"power":[106],"0.38":[108],"mW":[109,115],"at":[110,116,124,130,140,146],"0.9":[114],"jitter":[120],"8.8":[122],"ps":[123,129],"2.6":[128],"lock":[134],"time":[135],"40":[137],"clock":[138,144],"cycles":[139,145],"100MHz":[141],"24":[143]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}