{"id":"https://openalex.org/W2137876941","doi":"https://doi.org/10.1109/iscc.2003.1214175","title":"Evaluation of switch schedulers for embedded systems","display_name":"Evaluation of switch schedulers for embedded systems","publication_year":2004,"publication_date":"2004-03-30","ids":{"openalex":"https://openalex.org/W2137876941","doi":"https://doi.org/10.1109/iscc.2003.1214175","mag":"2137876941"},"language":"en","primary_location":{"id":"doi:10.1109/iscc.2003.1214175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscc.2003.1214175","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eighth IEEE Symposium on Computers and Communications. ISCC 2003","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027257996","display_name":"Dimitrios Serpanos","orcid":"https://orcid.org/0000-0002-1385-7113"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"D.N. Serpanos","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","Dept. of Electr. & Comput. Eng., Patras Univ., Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Patras Univ., Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047813446","display_name":"X. Moundrouidou","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"X. Moundrouidou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","Dept. of Electr. & Comput. Eng., Patras Univ., Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Patras Univ., Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016582977","display_name":"M. Gambrili","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"M. Gambrili","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","Dept. of Electr. & Comput. Eng., Patras Univ., Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Patras Univ., Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.2495,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67470085,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":null,"first_page":"541","last_page":"546"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8352972269058228},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.8072729110717773},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6536705493927002},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6175520420074463},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5409103631973267},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.520687460899353},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4619233310222626},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.41985630989074707},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4031684398651123},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.260661780834198},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19844648241996765},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07008892297744751}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8352972269058228},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.8072729110717773},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6536705493927002},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6175520420074463},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5409103631973267},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.520687460899353},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4619233310222626},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.41985630989074707},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4031684398651123},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.260661780834198},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19844648241996765},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07008892297744751},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscc.2003.1214175","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscc.2003.1214175","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eighth IEEE Symposium on Computers and Communications. ISCC 2003","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1591014349","https://openalex.org/W2016318026","https://openalex.org/W2044852445","https://openalex.org/W2111366547","https://openalex.org/W2112993274","https://openalex.org/W2126169247","https://openalex.org/W2142787641"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049","https://openalex.org/W2136848245"],"abstract_inverted_index":{"We":[0],"evaluate":[1],"hardware":[2,54],"and":[3,9,32,77],"software":[4,57],"implementations":[5,58],"of":[6,72],"a":[7,10,26],"centralized":[8,45],"distributed":[11,51,63],"scheduler":[12],"for":[13,21,59],"embedded":[14,22,60],"packet":[15],"switches.":[16],"The":[17,37],"evaluation":[18],"is":[19],"performed":[20],"system":[23,27],"implementation,":[24],"on":[25],"that":[28],"includes":[29],"an":[30,33],"FPGA":[31],"embedded,":[34],"on-chip":[35],"processor.":[36],"results":[38],"demonstrate":[39],"that,":[40],"in":[41,53],"contrast":[42],"to":[43,69],"expectations,":[44],"schedulers":[46,64],"provide":[47],"better":[48,66,70],"performance":[49],"than":[50],"ones":[52],"implementations.":[55],"In":[56],"processors,":[61],"surprisingly,":[62],"achieve":[65],"performance,":[67],"due":[68],"management":[71],"the":[73],"processor's":[74],"limited":[75],"resources":[76],"simpler":[78],"code.":[79]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}