{"id":"https://openalex.org/W7165206595","doi":"https://doi.org/10.1109/iscas66217.2026.11562976","title":"UMDAM: A Unified Data Layout and DRAM Address Mapping for Heterogeneous NPU-PIM","display_name":"UMDAM: A Unified Data Layout and DRAM Address Mapping for Heterogeneous NPU-PIM","publication_year":2026,"publication_date":"2026-05-24","ids":{"openalex":"https://openalex.org/W7165206595","doi":"https://doi.org/10.1109/iscas66217.2026.11562976"},"language":null,"primary_location":{"id":"doi:10.1109/iscas66217.2026.11562976","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas66217.2026.11562976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035875164","display_name":"H Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hai Huang","raw_affiliation_strings":["Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121385707","display_name":"Xuhong Qiang","orcid":null},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuhong Qiang","raw_affiliation_strings":["Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138945683","display_name":"Weisheng Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weisheng Zhao","raw_affiliation_strings":["Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100767202","display_name":"Chenchen Liu","orcid":"https://orcid.org/0000-0001-7749-0640"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenchen Liu","raw_affiliation_strings":["Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China","institution_ids":["https://openalex.org/I82880672"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I82880672"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"224","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.25839999318122864,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.25839999318122864,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.08839999884366989,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.06120000034570694,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4239000082015991},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.3280999958515167},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.27810001373291016},{"id":"https://openalex.org/keywords/data-modeling","display_name":"Data modeling","score":0.27320000529289246},{"id":"https://openalex.org/keywords/data-mapping","display_name":"Data mapping","score":0.2526000142097473}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6861000061035156},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4239000082015991},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.3294999897480011},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.3280999958515167},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.27810001373291016},{"id":"https://openalex.org/C67186912","wikidata":"https://www.wikidata.org/wiki/Q367664","display_name":"Data modeling","level":2,"score":0.27320000529289246},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2694999873638153},{"id":"https://openalex.org/C137314826","wikidata":"https://www.wikidata.org/wiki/Q2330408","display_name":"Data mapping","level":2,"score":0.2526000142097473},{"id":"https://openalex.org/C147494362","wikidata":"https://www.wikidata.org/wiki/Q2078905","display_name":"Troubleshooting","level":2,"score":0.24400000274181366},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.23549999296665192}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas66217.2026.11562976","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas66217.2026.11562976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2982008795","https://openalex.org/W2982219368","https://openalex.org/W3189166979","https://openalex.org/W4221001402","https://openalex.org/W4281644153","https://openalex.org/W4282551050","https://openalex.org/W4387064011","https://openalex.org/W4387064057","https://openalex.org/W4388757726","https://openalex.org/W4392427708","https://openalex.org/W4395073431","https://openalex.org/W4402475900","https://openalex.org/W4406163959","https://openalex.org/W4409248618","https://openalex.org/W4415799029"],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-06-19T00:00:00"}