{"id":"https://openalex.org/W7165160735","doi":"https://doi.org/10.1109/iscas66217.2026.11562568","title":"A 112Gb/s DAC-Based PAM-4 Transmitter with Fast Automatic Retiming Clock Phase Optimization and 6-Tap FFE in 28nm CMOS","display_name":"A 112Gb/s DAC-Based PAM-4 Transmitter with Fast Automatic Retiming Clock Phase Optimization and 6-Tap FFE in 28nm CMOS","publication_year":2026,"publication_date":"2026-05-24","ids":{"openalex":"https://openalex.org/W7165160735","doi":"https://doi.org/10.1109/iscas66217.2026.11562568"},"language":null,"primary_location":{"id":"doi:10.1109/iscas66217.2026.11562568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas66217.2026.11562568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053332589","display_name":"Chenxi Han","orcid":"https://orcid.org/0000-0003-4053-5897"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenxi Han","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138939541","display_name":"Huajin Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153682","display_name":"Intelligent Health (United Kingdom)","ror":"https://ror.org/0576zak10","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153682"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Huajin Sun","raw_affiliation_strings":["Jinan Maiwei Intelligent Technology Co., Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Jinan Maiwei Intelligent Technology Co., Ltd","institution_ids":["https://openalex.org/I4210153682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003457423","display_name":"Xiaoteng Zhao","orcid":"https://orcid.org/0000-0002-9447-8763"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoteng Zhao","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138860633","display_name":"Qi Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qi Zhang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138924116","display_name":"Yuan Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Liu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042803450","display_name":"Y W Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuhao Zhang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077372163","display_name":"Hongzhi Liang","orcid":"https://orcid.org/0000-0001-6609-9486"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongzhi Liang","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138942510","display_name":"Shubin Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5138917620","display_name":"Zhangming Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xidian University,Key Laboratory of Analog Integrated Circuits and Systems, Ministry of Education School of Integrated Circuits,Xi’an,China,710071","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"2066","last_page":"2070"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9775999784469604,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9775999784469604,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.006399999838322401,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00430000014603138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.52920001745224},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5109999775886536},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.3871999979019165},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.3237999975681305},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.2612000107765198}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6395999789237976},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.52920001745224},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5109999775886536},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4828000068664551},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.3871999979019165},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34439998865127563},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.3237999975681305},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2815000116825104},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.2612000107765198},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2547999918460846},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.25380000472068787},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25049999356269836}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas66217.2026.11562568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas66217.2026.11562568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8030158877372742}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2947208032","https://openalex.org/W3015484972","https://openalex.org/W3107847738","https://openalex.org/W3134707386","https://openalex.org/W3199786372","https://openalex.org/W3200274002","https://openalex.org/W4360606520","https://openalex.org/W4360607057","https://openalex.org/W4400927457","https://openalex.org/W4410492761"],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-06-19T00:00:00"}