{"id":"https://openalex.org/W4400231430","doi":"https://doi.org/10.1109/iscas58744.2024.10558595","title":"Novel SRAM based Temporary Memory for PVT Variation Tolerant Analog In-Memory Computing","display_name":"Novel SRAM based Temporary Memory for PVT Variation Tolerant Analog In-Memory Computing","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400231430","doi":"https://doi.org/10.1109/iscas58744.2024.10558595"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558595","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558595","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104341042","display_name":"Sivakumar Elangovan","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sivakumar Elangovan","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5099871391","display_name":"Porus Vangala","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Porus Vangala","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5099871392","display_name":"Yeshwanth Sunnapu","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Yeshwanth Sunnapu","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018462126","display_name":"Khalid Shaikh","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Khalid Shaikh","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073593093","display_name":"Udayan Ganguly","orcid":"https://orcid.org/0000-0002-1498-5993"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Udayan Ganguly","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029767607","display_name":"Maryam Shojaei Baghini","orcid":"https://orcid.org/0000-0001-6568-3736"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Maryam Shojaei Baghini","raw_affiliation_strings":["Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,Department of Electrical Engineering,Mumbai,India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.3632,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58073109,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9865000247955322,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9761000275611877,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7474919557571411},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7014409303665161},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5959573984146118},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5320984125137329},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.500140905380249},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.44951462745666504},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4353069067001343},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.41012513637542725},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34737104177474976},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3365382254123688},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24973320960998535},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23971223831176758}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7474919557571411},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7014409303665161},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5959573984146118},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5320984125137329},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.500140905380249},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.44951462745666504},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4353069067001343},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.41012513637542725},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34737104177474976},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3365382254123688},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24973320960998535},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23971223831176758}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558595","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558595","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2591601611","https://openalex.org/W2769224948","https://openalex.org/W2782511028","https://openalex.org/W2790556218","https://openalex.org/W2966878541","https://openalex.org/W2969812992","https://openalex.org/W3015432327","https://openalex.org/W3089015596","https://openalex.org/W3134244351","https://openalex.org/W3161810489","https://openalex.org/W3180627186","https://openalex.org/W3194056411","https://openalex.org/W4226402784"],"related_works":["https://openalex.org/W4232117715","https://openalex.org/W1977963439","https://openalex.org/W4234756210","https://openalex.org/W4285257158","https://openalex.org/W2185519377","https://openalex.org/W3209704453","https://openalex.org/W2024190459","https://openalex.org/W2546565930","https://openalex.org/W2065778483","https://openalex.org/W1992635254"],"abstract_inverted_index":{"Analog":[0],"in-memory":[1,72],"computing":[2,45],"(IMC)":[3],"techniques":[4],"have":[5],"played":[6],"a":[7,60,102,125],"significant":[8],"role":[9],"in":[10,41],"vastly":[11],"improving":[12],"the":[13,26,31,96,132],"throughput,":[14],"energy":[15,89],"efficiency,":[16],"and":[17,37],"area":[18],"of":[19,50,108,116,124],"on-chip":[20],"ML":[21,47],"inference":[22,48],"engines,":[23],"breaking":[24],"through":[25],"Von-Neumann":[27],"memory":[28,68,99],"bottleneck.":[29],"However,":[30],"innate":[32],"susceptibility":[33],"to":[34,46,52,81],"process,":[35],"voltage":[36],"temperature":[38],"(PVT)":[39],"variations":[40],"effect":[42],"restricts":[43],"analog":[44,71],"applications":[49],"low":[51],"moderate":[53],"complexity.":[54],"In":[55],"this":[56],"work,":[57],"we":[58],"present":[59],"novel":[61],"PVT":[62],"variation":[63],"tolerant":[64],"SRAM":[65],"based":[66],"temporary":[67,98],"(STEM)":[69],"for":[70],"computing.":[73],"The":[74],"proposed":[75,97,133],"technique":[76],"also":[77],"allows":[78],"unit":[79,103,119],"cells":[80],"operate":[82],"at":[83],"ultralow":[84],"currents,":[85],"thereby":[86],"enabling":[87],"better":[88,113],"efficiency.":[90],"Monte":[91],"Carlo":[92],"simulations":[93,123],"show":[94,130],"that":[95,115,131],"array":[100],"achieves":[101,135],"cell":[104],"current":[105],"variability":[106],"(\u03c3/\u03bc)":[107],"2%":[109],"which":[110],"is":[111],"5\u00d7":[112],"than":[114],"conventional":[117],"8T":[118],"cell.":[120],"System":[121],"level":[122],"64":[126,128],"\u00d7":[127],"macro":[129],"STEM":[134],"near":[136],"baseline":[137],"classification":[138],"accuracy":[139],"on":[140],"FMNIST":[141],"dataset":[142],"using":[143],"pre-trained":[144],"weights,":[145],"without":[146],"chip-specific":[147],"training.":[148]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
