{"id":"https://openalex.org/W4400232357","doi":"https://doi.org/10.1109/iscas58744.2024.10558541","title":"A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits","display_name":"A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400232357","doi":"https://doi.org/10.1109/iscas58744.2024.10558541"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558541","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558541","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101896871","display_name":"Zhikai Wang","orcid":"https://orcid.org/0000-0003-0852-2658"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhikai Wang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112436964","display_name":"Zuochang Ye","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zuochang Ye","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101481194","display_name":"Jingbo Zhou","orcid":"https://orcid.org/0000-0003-2677-7021"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jingbo Zhou","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052857735","display_name":"Xiaosen Liu","orcid":"https://orcid.org/0000-0003-2767-215X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiaosen Liu","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5101846033","display_name":"Yan Wang","orcid":"https://orcid.org/0000-0003-4309-3166"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yan Wang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3542,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.77764924,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9853000044822693,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9853000044822693,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9801999926567078,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9695000052452087,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.6896620988845825},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6644206047058105},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6151271462440491},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5928486585617065},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5721558332443237},{"id":"https://openalex.org/keywords/radio-frequency","display_name":"Radio frequency","score":0.5152947902679443},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5088841915130615},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.44779515266418457},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3590904176235199},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29891252517700195},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19722691178321838},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1453777253627777},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06504848599433899}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.6896620988845825},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6644206047058105},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6151271462440491},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5928486585617065},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5721558332443237},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.5152947902679443},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5088841915130615},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.44779515266418457},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3590904176235199},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29891252517700195},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19722691178321838},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1453777253627777},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06504848599433899},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558541","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558541","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1522301498","https://openalex.org/W2074046446","https://openalex.org/W2075695749","https://openalex.org/W2111776955","https://openalex.org/W2113068346","https://openalex.org/W2130265872","https://openalex.org/W2136848459","https://openalex.org/W2532972346","https://openalex.org/W2588897393","https://openalex.org/W2799969132","https://openalex.org/W2913707927","https://openalex.org/W2998328510","https://openalex.org/W3036532492","https://openalex.org/W3160469020","https://openalex.org/W3166315890","https://openalex.org/W4200312391","https://openalex.org/W4231324143","https://openalex.org/W4236728296","https://openalex.org/W4243099375","https://openalex.org/W4300118013","https://openalex.org/W6631190155","https://openalex.org/W6787067255","https://openalex.org/W6844076591"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2375192119","https://openalex.org/W2107461746","https://openalex.org/W2146537238","https://openalex.org/W2076146297","https://openalex.org/W4237705761","https://openalex.org/W2168223448","https://openalex.org/W2169238810"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3],"two-step":[4,55],"fine-tuning":[5],"assisted":[6],"layout":[7],"sizing":[8],"(FALS)":[9],"scheme":[10],"with":[11,29,71],"an":[12],"efficient":[13],"post-layout":[14],"sampling":[15],"feature,":[16],"the":[17,47,52,78],"key":[18],"of":[19,54],"which":[20],"is":[21,43,46],"to":[22,50],"reuse":[23],"abundant":[24],"and":[25,37,57],"cheap":[26],"schematic":[27],"information":[28],"Transfer":[30],"Learning":[31],"for":[32],"quickly":[33],"pruning":[34],"design":[35],"space":[36],"achieving":[38],"global":[39],"optimization.":[40,61],"The":[41,62],"innovation":[42],"that":[44],"FALS":[45,70],"first":[48],"work":[49],"integrate":[51],"advantages":[53],"optimization":[56,64],"high-accuracy":[58],"model-based":[59],"local":[60],"same":[63],"results":[65],"can":[66],"be":[67],"achieved":[68],"by":[69],"significantly":[72],"10\u00d7":[73],"less":[74],"total":[75],"run-time":[76],"than":[77],"conventional":[79],"DE.":[80]},"counts_by_year":[{"year":2025,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}