{"id":"https://openalex.org/W4400229759","doi":"https://doi.org/10.1109/iscas58744.2024.10558524","title":"Explainable automated data estimation in Logic State Imaging of embedded SRAM","display_name":"Explainable automated data estimation in Logic State Imaging of embedded SRAM","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400229759","doi":"https://doi.org/10.1109/iscas58744.2024.10558524"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558524","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10558524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077877722","display_name":"Samuel Chef","orcid":"https://orcid.org/0000-0002-1729-7432"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Samuel Chef","raw_affiliation_strings":["Nanyang Technological University,Temasek Laboratories@NTU,Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University,Temasek Laboratories@NTU,Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108644153","display_name":"Chung Tah Chua","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Chung Tah Chua","raw_affiliation_strings":["Nanyang Technological University,Temasek Laboratories@NTU,Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University,Temasek Laboratories@NTU,Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111246024","display_name":"Jing Yun Tay","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Jing Yun Tay","raw_affiliation_strings":["Nanyang Technological University,Temasek Laboratories@NTU,Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University,Temasek Laboratories@NTU,Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006684936","display_name":"Chee Lip Gan","orcid":"https://orcid.org/0000-0002-8420-3168"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Chee Lip Gan","raw_affiliation_strings":["Nanyang Technological University,Temasek Laboratories@NTU,Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University,Temasek Laboratories@NTU,Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5077877722"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07290518,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2018","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7486928701400757},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6735272407531738},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.514991819858551},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.46427032351493835},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4541563093662262},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3891000747680664},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34591203927993774},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3104977309703827},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2025742530822754},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1367797553539276},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.09041273593902588}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7486928701400757},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6735272407531738},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.514991819858551},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.46427032351493835},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4541563093662262},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3891000747680664},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34591203927993774},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3104977309703827},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2025742530822754},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1367797553539276},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.09041273593902588}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558524","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10558524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1631035314","https://openalex.org/W1976117316","https://openalex.org/W2008056655","https://openalex.org/W2099247250","https://openalex.org/W2101091565","https://openalex.org/W2299467264","https://openalex.org/W2479752304","https://openalex.org/W2535614716","https://openalex.org/W2766071343","https://openalex.org/W2808601176","https://openalex.org/W2891421382","https://openalex.org/W2921795960","https://openalex.org/W3045547591","https://openalex.org/W3045751739","https://openalex.org/W3045773521","https://openalex.org/W3193317785","https://openalex.org/W3197312262","https://openalex.org/W4312966603","https://openalex.org/W6776294083","https://openalex.org/W6790418948"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W2109451123","https://openalex.org/W4378977321","https://openalex.org/W1976168335","https://openalex.org/W4308090481","https://openalex.org/W3211992815","https://openalex.org/W179354024"],"abstract_inverted_index":{"Semi-invasive":[0],"logic":[1],"state":[2],"imaging":[3],"of":[4,30,41,51,67,84,93],"SRAM":[5],"cells":[6],"via":[7],"optical":[8,101],"analysis":[9],"has":[10],"been":[11],"demonstrated":[12],"to":[13,25,81,111],"be":[14],"a":[15,61,122,130],"powerful":[16],"attack":[17],"vector":[18],"on":[19,27,74,121,129],"advanced":[20],"ICs.":[21],"Reported":[22],"applications":[23],"tend":[24],"focus":[26],"the":[28,39,64],"recovery":[29,106],"small":[31],"size":[32,53],"secrets":[33],"such":[34,94],"as":[35],"encryption":[36,46],"keys.":[37],"However,":[38],"emergence":[40],"new":[42],"cryptographic":[43],"algorithms":[44],"with":[45],"keys":[47],"or":[48],"other":[49],"assets":[50],"larger":[52],"makes":[54,100],"manual":[55],"approach":[56,96,118],"challenging.":[57],"In":[58],"this":[59],"manuscript,":[60],"framework":[62],"for":[63,103],"automated":[65],"estimation":[66],"bitcell":[68],"data":[69,114],"is":[70,97,115,119],"developed.":[71],"It":[72],"focuses":[73],"understanding":[75],"signal":[76],"generation":[77],"and":[78,87],"detection":[79],"processes":[80],"assess":[82],"viability":[83],"well-established":[85],"classification":[86],"clustering":[88],"algorithms.":[89],"A":[90],"main":[91],"advantage":[92],"an":[95],"that":[98],"it":[99],"attacks":[102],"large":[104],"scale":[105],"more":[107],"feasible":[108],"since":[109],"limited":[110],"no":[112],"training":[113],"required.":[116],"The":[117],"evaluated":[120],"dataset":[123],"generated":[124],"under":[125],"Thermal":[126],"Laser":[127],"Stimulation":[128],"commercial":[131],"SoC-FPGA":[132],"manufactured":[133],"in":[134],"28":[135],"nm":[136],"technology.":[137]},"counts_by_year":[],"updated_date":"2025-12-26T23:08:49.675405","created_date":"2025-10-10T00:00:00"}