{"id":"https://openalex.org/W4400230155","doi":"https://doi.org/10.1109/iscas58744.2024.10558173","title":"Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks","display_name":"Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400230155","doi":"https://doi.org/10.1109/iscas58744.2024.10558173"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558173","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10558173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043895547","display_name":"G. Li\u00f1\u00e1n","orcid":"https://orcid.org/0000-0003-1839-555X"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Gustavo Li\u00f1\u00e1n-Cembrano","raw_affiliation_strings":["IMSE-CNM (CSIC/Universidad de Sevilla),Instituto de Microelectr&#x00F3;nica de Sevilla,Sevilla,Spain,41092"],"affiliations":[{"raw_affiliation_string":"IMSE-CNM (CSIC/Universidad de Sevilla),Instituto de Microelectr&#x00F3;nica de Sevilla,Sevilla,Spain,41092","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042960119","display_name":"Jos\u00e9 M. de la Rosa","orcid":"https://orcid.org/0000-0003-2848-9226"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 M. De La Rosa","raw_affiliation_strings":["IMSE-CNM (CSIC/Universidad de Sevilla),Instituto de Microelectr&#x00F3;nica de Sevilla,Sevilla,Spain,41092"],"affiliations":[{"raw_affiliation_string":"IMSE-CNM (CSIC/Universidad de Sevilla),Instituto de Microelectr&#x00F3;nica de Sevilla,Sevilla,Spain,41092","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5043895547"],"corresponding_institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08881727,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9265000224113464,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9265000224113464,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9253000020980835,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.7931128144264221},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6852649450302124},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6011964678764343},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5699548125267029},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46389034390449524},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.45330461859703064},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.4278995394706726},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35862457752227783},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34557467699050903},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32054686546325684},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23750042915344238},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.21571290493011475},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20058152079582214},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.19339272379875183},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16931894421577454},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08719757199287415}],"concepts":[{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.7931128144264221},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6852649450302124},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6011964678764343},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5699548125267029},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46389034390449524},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.45330461859703064},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.4278995394706726},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35862457752227783},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34557467699050903},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32054686546325684},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23750042915344238},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.21571290493011475},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20058152079582214},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.19339272379875183},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16931894421577454},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08719757199287415},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558173","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10558173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2886810525","https://openalex.org/W4385245043","https://openalex.org/W4387546396"],"related_works":["https://openalex.org/W4242258007","https://openalex.org/W2185815555","https://openalex.org/W2375192119","https://openalex.org/W2053330176","https://openalex.org/W1981652693","https://openalex.org/W2076925294","https://openalex.org/W1162056860","https://openalex.org/W1862020018","https://openalex.org/W2109999133","https://openalex.org/W2498536136"],"abstract_inverted_index":{"This":[0],"demo":[1,113],"shows":[2],"how":[3],"to":[4,26,33,77,97],"use":[5],"Artificial":[6],"Neural":[7],"Networks":[8],"(ANNs)":[9],"for":[10,83,117],"the":[11,28,63,99,112,118],"optimization":[12,46,119],"and":[13,18,30,45,108,124,128],"automated":[14],"design":[15,81,101],"of":[16,47,66,87,102,120],"analog":[17,123],"mixed-signal":[19,125],"circuits.":[20],"A":[21],"step-by-step":[22],"procedure":[23],"is":[24,62],"demonstrated":[25],"explain":[27],"key":[29],"practical":[31],"aspects":[32],"consider":[34],"in":[35,111],"this":[36],"approach,":[37],"such":[38],"as":[39],"dataset":[40],"preparation,":[41],"ANNs":[42,71,93],"modeling,":[43],"training,":[44],"network":[48],"hyperparameters.":[49],"Two":[50],"case":[51],"studies":[52],"at":[53],"different":[54],"abstraction":[55],"levels":[56],"are":[57,72],"presented.":[58],"The":[59,89,106],"first":[60],"one":[61],"system-level":[64],"sizing":[65],"Sigma-Delta":[67],"Modulators":[68],"(\u03a3\u2206Ms),":[69],"where":[70],"combined":[73],"with":[74,94],"behavioral":[75],"simulations":[76],"generate":[78],"valid":[79],"circuit-level":[80,100],"variables":[82],"a":[84],"given":[85],"set":[86],"specifications.":[88],"second":[90],"example":[91],"combines":[92],"electrical":[95],"simulators":[96],"optimize":[98],"operational":[103],"transconductance":[104],"amplifiers.":[105],"methods":[107],"tools":[109],"shown":[110],"can":[114],"be":[115],"used":[116],"any":[121],"arbitrary":[122],"integrated":[126],"circuits":[127],"systems":[129],"<sup":[130],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[131],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sup>.ISCAS":[132],"Track:":[133],"Analog":[134],"Signal":[135],"Processing.":[136]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}