{"id":"https://openalex.org/W4400235383","doi":"https://doi.org/10.1109/iscas58744.2024.10558064","title":"Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions","display_name":"Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400235383","doi":"https://doi.org/10.1109/iscas58744.2024.10558064"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073808784","display_name":"Dongzhu Li","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Dongzhu Li","raw_affiliation_strings":["The University of Tokyo,Graduate School of Engineering,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Graduate School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059850130","display_name":"Tianqi Zhao","orcid":"https://orcid.org/0000-0002-3562-4679"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianqi Zhao","raw_affiliation_strings":["Tsinghua University,Department of Electronic Engineering,Beijing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University,Department of Electronic Engineering,Beijing,China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087683697","display_name":"Kenji Kobayashi","orcid":"https://orcid.org/0000-0002-9312-7857"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenji Kobayashi","raw_affiliation_strings":["The University of Tokyo,Graduate School of Engineering,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Graduate School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054228824","display_name":"Atsutake Kosuge","orcid":"https://orcid.org/0000-0002-3394-2227"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsutake Kosuge","raw_affiliation_strings":["The University of Tokyo,Graduate School of Engineering,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Graduate School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068257959","display_name":"Mototsugu Hamada","orcid":"https://orcid.org/0000-0002-0461-4208"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mototsugu Hamada","raw_affiliation_strings":["The University of Tokyo,Graduate School of Engineering,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Graduate School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073154009","display_name":"Tadahiro Kuroda","orcid":"https://orcid.org/0000-0003-0617-1057"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tadahiro Kuroda","raw_affiliation_strings":["The University of Tokyo,Graduate School of Engineering,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Graduate School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3542,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.77834336,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9890999794006348,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9890999794006348,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.980400025844574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8231341242790222},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6857268810272217},{"id":"https://openalex.org/keywords/segmentation","display_name":"Segmentation","score":0.6131521463394165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41802626848220825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41373923420906067},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3763488829135895},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33866041898727417},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18560418486595154},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1759870946407318}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8231341242790222},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6857268810272217},{"id":"https://openalex.org/C89600930","wikidata":"https://www.wikidata.org/wiki/Q1423946","display_name":"Segmentation","level":2,"score":0.6131521463394165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41802626848220825},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41373923420906067},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3763488829135895},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33866041898727417},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18560418486595154},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1759870946407318}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1999085092","https://openalex.org/W2585560244","https://openalex.org/W3205657855","https://openalex.org/W4206713916","https://openalex.org/W4220764408","https://openalex.org/W4226209055","https://openalex.org/W4297097387","https://openalex.org/W4384947529","https://openalex.org/W4385192610","https://openalex.org/W6810670354"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2373535795","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"A":[0],"coarse-":[1],"and":[2,89,115,118,160,176],"fine-grained":[3],"lookup":[4],"table":[5],"(LUT)":[6],"segmentation":[7,110],"technique":[8,111],"is":[9,189],"developed":[10],"for":[11,62,167,183,196],"wired-logic":[12,27,136],"artificial":[13],"intelligence":[14],"(AI)":[15],"processors":[16,28,45,137],"to":[17,134],"improve":[18],"field-programmable":[19],"gate":[20],"array":[21],"(FPGA)":[22],"resource":[23,165],"utilization":[24],"efficiency.":[25],"While":[26],"have":[29],"achieved":[30],"several":[31],"orders":[32],"of":[33,93,100,125,130,142,150],"magnitude":[34],"higher":[35],"energy":[36],"efficiency":[37],"than":[38],"conventional":[39],"FPGA-based":[40],"deep":[41],"neural":[42,95,152],"network":[43],"(DNN)":[44],"on":[46,113],"the":[47,63,78,91,98,123,140,148,180,197],"CIFAR-10":[48,158,184],"dataset":[49],"by":[50,174,201],"eliminating":[51],"DRAM/BRAM":[52],"access":[53],"during":[54],"inference":[55],"processing,":[56],"huge":[57],"hardware":[58,79,164],"resources":[59,80],"are":[60,105],"required":[61],"large-scale":[64],"DNNs":[65,72],"with":[66],"long-bit-width":[67,101],"data.":[68],"Implementing":[69],"even":[70],"small":[71,192],"proves":[73],"challenging":[74],"as":[75],"they":[76],"surpass":[77],"available":[81],"in":[82,170,194],"commercial":[83],"FPGAs.":[84],"To":[85],"address":[86],"these":[87,131],"issues":[88],"enable":[90],"implementation":[92,149],"larger-scale":[94,151],"networks":[96,153],"alongside":[97],"processing":[99,171],"data,":[102],"two":[103],"techniques":[104,133],"proposed:":[106],"(1)":[107],"an":[108],"LUT":[109],"based":[112],"coarse":[114],"fine":[116],"granularity,":[117],"(2)":[119],"accuracy":[120,182,195],"optimization":[121],"through":[122],"incorporation":[124],"redundant":[126],"bits.":[127],"The":[128,163],"application":[129],"proposed":[132],"state-of-the-art":[135],"markedly":[138],"enhances":[139],"scalability":[141],"a":[143,190],"single":[144],"FPGA,":[145],"thereby":[146],"facilitating":[147],"across":[154],"various":[155],"tasks,":[156],"including":[157],"classification":[159],"keyword":[161,198],"spotting.":[162],"requirements":[166],"non-linear":[168],"functions":[169],"elements":[172],"decreased":[173],"92%,":[175],"92.8%,":[177],"respectively.":[178],"Remarkably,":[179],"recognition":[181],"remains":[185],"consistent,":[186],"while":[187],"there":[188],"negligibly":[191],"degradation":[193],"spotting":[199],"task":[200],"1.2%.":[202]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
