{"id":"https://openalex.org/W4400230584","doi":"https://doi.org/10.1109/iscas58744.2024.10558054","title":"SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin","display_name":"SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400230584","doi":"https://doi.org/10.1109/iscas58744.2024.10558054"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10558054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081698284","display_name":"Dinesh Kushwaha","orcid":"https://orcid.org/0000-0003-3446-5909"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Dinesh Kushwaha","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105554115","display_name":"Rajiv Joshi","orcid":"https://orcid.org/0009-0007-7486-1531"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rajiv V. Joshi","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064560509","display_name":"Sudeb Dasgupta","orcid":"https://orcid.org/0000-0002-4044-1594"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sudeb Dasgupta","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5031850929","display_name":"Anand Bulusu","orcid":"https://orcid.org/0000-0002-3986-3730"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anand Bulusu","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5081698284"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6674,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6847866,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7914641499519348},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7064881324768066},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.6591984033584595},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5372697114944458},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5228110551834106},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.48256435990333557},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4805615246295929},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44305911660194397},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39322027564048767},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38873225450515747},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36395835876464844},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34263211488723755},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11600509285926819}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7914641499519348},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7064881324768066},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.6591984033584595},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5372697114944458},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5228110551834106},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.48256435990333557},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4805615246295929},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44305911660194397},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39322027564048767},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38873225450515747},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36395835876464844},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34263211488723755},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11600509285926819},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10558054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas58744.2024.10558054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W2591601611","https://openalex.org/W2782511028","https://openalex.org/W2904299207","https://openalex.org/W3016021860","https://openalex.org/W3017968097","https://openalex.org/W3097655915","https://openalex.org/W3134244351","https://openalex.org/W3139521791","https://openalex.org/W3163974534","https://openalex.org/W4206066474","https://openalex.org/W4210923376","https://openalex.org/W4214833843","https://openalex.org/W4226402784","https://openalex.org/W4226477664","https://openalex.org/W4285676410","https://openalex.org/W4296704900","https://openalex.org/W4312978570","https://openalex.org/W4313639541","https://openalex.org/W4364296667","https://openalex.org/W4376456681","https://openalex.org/W4383501736","https://openalex.org/W4385267238","https://openalex.org/W4388145418"],"related_works":["https://openalex.org/W2089002058","https://openalex.org/W1909296377","https://openalex.org/W3185029353","https://openalex.org/W3116379964","https://openalex.org/W2766443086","https://openalex.org/W2915176329","https://openalex.org/W2793465010","https://openalex.org/W2967161359","https://openalex.org/W2208608937","https://openalex.org/W2032691814"],"abstract_inverted_index":{"This":[0,15],"manuscript":[1],"proposes":[2],"an":[3],"SRAM-based":[4],"hybrid":[5,16],"analog":[6],"compute-in-memory":[7],"(CIM)":[8],"architecture":[9,17,82,102,150],"to":[10,91],"enhance":[11],"the":[12,39,55,59,63,77,92,100,127,131,135],"signal":[13,88],"margin.":[14],"presents":[18],"fully":[19],"differential":[20],"current-based":[21,56],"and":[22,26,48,70,97,106,115,130,137,144,157],"C-2C":[23],"charge-sharing-based":[24],"multiplication":[25],"accumulation":[27],"(MAC)":[28],"CIM":[29],"schemes":[30],"for":[31,134,153],"4-bit":[32],"MAC":[33,36,60,155],"operation.":[34],"The":[35,80,94,148],"operation":[37,61,156],"of":[38,62,99],"filter":[40],"weight's":[41],"least":[42],"significant":[43,65],"bits":[44,66],"(w<inf":[45,67],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[46,50,68,72],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">0</inf>":[47],"w<inf":[49,71],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</inf>)":[51],"is":[52,74,124,141,151],"implemented":[53,75,125,158],"in":[54,76,87,159],"CIM.":[57,79],"However,":[58],"most":[64],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>":[69],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">3</inf>)":[73],"charge-based":[78],"proposed":[81,101,128,149],"achieves":[83],"a":[84],"4.37\u00d7":[85],"enhancement":[86],"margin":[89],"compared":[90],"state-of-the-art.":[93],"energy":[95],"efficiency":[96],"throughput":[98],"are":[103],"1551.5":[104],"TOPS/W":[105],"512":[107],"GOPS,":[108],"respectively,":[109],"at":[110],"0.9":[111],"V":[112],"supply":[113],"voltage":[114],"250":[116],"MHz":[117],"frequency.":[118],"A":[119],"convolutional":[120],"neural":[121],"network":[122],"(CNN)":[123],"on":[126],"architecture,":[129],"inference":[132],"accuracy":[133],"MNIST":[136],"CIFAR-10":[138],"data":[139],"sets":[140],"98.6":[142],"%":[143],"86":[145],"%,":[146],"respectively.":[147],"scalable":[152],"multi-bit":[154],"28":[160],"nm":[161],"CMOS":[162],"technology.":[163]},"counts_by_year":[{"year":2025,"cited_by_count":3}],"updated_date":"2025-12-21T23:12:01.093139","created_date":"2025-10-10T00:00:00"}