{"id":"https://openalex.org/W4400230326","doi":"https://doi.org/10.1109/iscas58744.2024.10557930","title":"A Data-Distribution Aware Approximate Multiplier Design Based on FPGA","display_name":"A Data-Distribution Aware Approximate Multiplier Design Based on FPGA","publication_year":2024,"publication_date":"2024-05-19","ids":{"openalex":"https://openalex.org/W4400230326","doi":"https://doi.org/10.1109/iscas58744.2024.10557930"},"language":"en","primary_location":{"id":"doi:10.1109/iscas58744.2024.10557930","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10557930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006106159","display_name":"Mingyu Shu","orcid":"https://orcid.org/0009-0000-9221-7669"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingyu Shu","raw_affiliation_strings":["Tianjin University,School of Microelectronics,Tianjin,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tianjin University,School of Microelectronics,Tianjin,China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033160150","display_name":"Yingchang Mao","orcid":"https://orcid.org/0000-0002-2731-3571"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yingchang Mao","raw_affiliation_strings":["Tianjin University,School of Microelectronics,Tianjin,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tianjin University,School of Microelectronics,Tianjin,China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100409523","display_name":"Qiang Liu","orcid":"https://orcid.org/0000-0003-1375-0508"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Liu","raw_affiliation_strings":["Tianjin University,School of Microelectronics,Tianjin,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tianjin University,School of Microelectronics,Tianjin,China","institution_ids":["https://openalex.org/I162868743"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162868743"],"apc_list":null,"apc_paid":null,"fwci":2.5131,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.88727686,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.8730000257492065,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.8730000257492065,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13717","display_name":"Advanced Algorithms and Applications","score":0.8317999839782715,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7955999970436096,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7845627069473267},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.690295934677124},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5710958242416382},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3468957841396332},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3404301702976227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32756179571151733}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7845627069473267},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.690295934677124},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5710958242416382},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3468957841396332},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3404301702976227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32756179571151733},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas58744.2024.10557930","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas58744.2024.10557930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2612139336","https://openalex.org/W2767737961","https://openalex.org/W2786234252","https://openalex.org/W2808908725","https://openalex.org/W2986165447","https://openalex.org/W3004524066","https://openalex.org/W3013744920","https://openalex.org/W3018203643","https://openalex.org/W3092362650","https://openalex.org/W3126267573","https://openalex.org/W3195415980","https://openalex.org/W4293173892","https://openalex.org/W4311839887","https://openalex.org/W4311839916","https://openalex.org/W4312641555","https://openalex.org/W4381329409"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"The":[0,82],"approximate":[1,28,94],"multiplier":[2,29,119],"(AM)":[3],"serves":[4],"as":[5],"a":[6,25,36,50,78],"computing":[7],"unit":[8],"that":[9,66],"saves":[10],"hardware":[11],"resources":[12],"and":[13,134],"power":[14],"consumption":[15],"at":[16],"the":[17,57,60,86,116,129],"expense":[18],"of":[19,45,59,77],"computational":[20],"accuracy.":[21],"This":[22],"paper":[23],"proposes":[24],"data-distribution":[26],"aware":[27],"(DDAM)":[30],"design":[31,42,71],"for":[32,40],"FPGAs.":[33],"We":[34],"build":[35],"numerical":[37],"optimization":[38,61],"model":[39],"automatic":[41],"space":[43],"exploration":[44,72],"DDAM.":[46],"Furthermore,":[47,100],"we":[48],"propose":[49],"weight-based":[51],"iterative":[52],"algorithm":[53],"(WIA)":[54],"to":[55,74,93,115,123],"accelerate":[56],"solution":[58],"model.":[62],"Experimental":[63],"results":[64],"demonstrate":[65],"WIA":[67],"significantly":[68],"reduces":[69,85,109],"DDAM":[70,84,108,127],"time":[73],"approximately":[75],"0.05%":[76],"generic":[79],"search":[80],"method.":[81],"generated":[83],"average":[87],"error":[88],"by":[89,112],"about":[90],"43%":[91],"compared":[92,114],"multipliers":[95],"with":[96],"uniform":[97],"data":[98],"distribution.":[99],"in":[101],"an":[102],"8":[103,105],"\u00d7":[104],"multiplication":[106],"scenario,":[107],"LUT":[110],"utilization":[111],"48%":[113],"Xilinx\u2019s":[117],"accurate":[118],"IP":[120],"core.":[121],"Compared":[122],"existing":[124],"FPGA-based":[125],"AMs,":[126],"achieves":[128],"best":[130],"balance":[131],"between":[132],"accuracy":[133],"area.":[135]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1}],"updated_date":"2026-08-11T07:18:39.950985","created_date":"2025-10-10T00:00:00"}
