{"id":"https://openalex.org/W4411725465","doi":"https://doi.org/10.1109/iscas56072.2025.11044291","title":"C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs","display_name":"C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725465","doi":"https://doi.org/10.1109/iscas56072.2025.11044291"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11044291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Ritwik Basyas Goswami","orcid":null},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ritwik Basyas Goswami","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019957161","display_name":"Mohammad Rehan Akhtar","orcid":"https://orcid.org/0000-0001-8927-8655"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mohammad Rehan Akhtar","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109414323","display_name":"Andleeb Zahra","orcid":null},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Andleeb Zahra","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060396811","display_name":"Zia Abbas","orcid":"https://orcid.org/0000-0002-3747-3640"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Zia Abbas","raw_affiliation_strings":["International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology, Hyderabad (IIIT-H),Centre for VLSI and Embedded Systems Technology (CVEST),Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14865788,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9764000177383423,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.941100001335144,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/foundation","display_name":"Foundation (evidence)","score":0.6530000567436218},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6241868138313293},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5807842016220093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5243104696273804},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4875349700450897},{"id":"https://openalex.org/keywords/arch","display_name":"Arch","score":0.4673350751399994},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4539106786251068},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3559076189994812},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32990407943725586},{"id":"https://openalex.org/keywords/structural-engineering","display_name":"Structural engineering","score":0.11221423745155334}],"concepts":[{"id":"https://openalex.org/C2780966255","wikidata":"https://www.wikidata.org/wiki/Q5474306","display_name":"Foundation (evidence)","level":2,"score":0.6530000567436218},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6241868138313293},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5807842016220093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5243104696273804},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4875349700450897},{"id":"https://openalex.org/C11312509","wikidata":"https://www.wikidata.org/wiki/Q12277","display_name":"Arch","level":2,"score":0.4673350751399994},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4539106786251068},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3559076189994812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32990407943725586},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.11221423745155334},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11044291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W28412257","https://openalex.org/W1968204888","https://openalex.org/W1982303956","https://openalex.org/W2100128988","https://openalex.org/W2115834537","https://openalex.org/W2194775991","https://openalex.org/W2789758093","https://openalex.org/W2803002867","https://openalex.org/W2914369697","https://openalex.org/W3016286676","https://openalex.org/W3091131165","https://openalex.org/W3164008977","https://openalex.org/W4229455242","https://openalex.org/W4310256192","https://openalex.org/W4380894245","https://openalex.org/W4400231453","https://openalex.org/W6736057607","https://openalex.org/W6742288159","https://openalex.org/W6745609711","https://openalex.org/W6857301720","https://openalex.org/W7006806681"],"related_works":["https://openalex.org/W2351700194","https://openalex.org/W1813077521","https://openalex.org/W2370180072","https://openalex.org/W3168322612","https://openalex.org/W42916264","https://openalex.org/W2752343614","https://openalex.org/W4232040869","https://openalex.org/W1958423747","https://openalex.org/W2003640865","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Modeling":[0],"process,":[1],"operating":[2,61],"condition,":[3],"reliability,":[4],"and":[5,17,45,52,69,79,83,130,142,157],"technological":[6],"variation":[7],"in":[8,15,48,107,144,162],"transistor":[9],"level":[10],"design":[11],"introduce":[12],"significant":[13],"variance":[14,106],"device":[16],"performance":[18,92],"parameters.":[19],"This":[20],"paper":[21],"presents":[22],"a":[23,32,98,113],"machine-learning-based":[24],"architectural":[25],"approach":[26],"that":[27],"enhances":[28],"model":[29],"performance,":[30],"as":[31,112],"step":[33],"towards":[34],"developing":[35],"Foundation":[36,160],"Models":[37,161],"tailored":[38],"for":[39,116],"circuit":[40,117,163],"data,":[41],"accurately":[42],"capturing":[43],"technology":[44,87],"process-induced":[46],"variations":[47],"leakage":[49,131],"power,":[50],"voltage,":[51,129],"current.":[53],"The":[54],"architecture":[55,100],"incorporates":[56],"the":[57,91,104,120,154],"impact":[58],"of":[59,73,93,137,159],"varying":[60],"conditions,":[62],"including":[63],"temperatures":[64],"from":[65],"-55\u00b0C":[66],"to":[67,101,103,139,150],"125\u00b0C":[68],"supply":[70],"voltage":[71],"fluctuations":[72],"\u00b110%":[74],"on":[75,127],"16nm":[76],"HP":[77],"FinFET,":[78],"16nm,":[80],"22nm,":[81],"32nm,":[82],"45nm":[84],"HP-MGK":[85],"CMOS":[86],"nodes.":[88],"By":[89],"enhancing":[90],"baseline":[94,151],"machine-learning":[95],"models":[96],"using":[97],"chained":[99],"cater":[102],"high":[105],"target,":[108],"our":[109],"C-Arch":[110],"serves":[111],"versatile":[114],"framework":[115],"modeling":[118],"when":[119],"data":[121],"spread":[122],"is":[123],"high.":[124],"Experimental":[125],"results":[126],"current,":[128],"power":[132],"estimation,":[133],"demonstrate":[134],"average":[135],"improvements":[136],"up":[138],"93.76%,":[140],"96.17%,":[141],"88.82%":[143],"Mean":[145],"Absolute":[146],"Percentage":[147],"Error":[148],"compared":[149],"models,":[152],"underscoring":[153],"computational":[155],"savings":[156],"viability":[158],"design.":[164]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
