{"id":"https://openalex.org/W4411725801","doi":"https://doi.org/10.1109/iscas56072.2025.11044179","title":"Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem","display_name":"Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725801","doi":"https://doi.org/10.1109/iscas56072.2025.11044179"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11044179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.manchester.ac.uk/en/publications/4581bd69-527e-4a43-a327-c079e69faa5e","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014928358","display_name":"Marcin Lewandowski","orcid":"https://orcid.org/0000-0001-8668-8368"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Maciej Lewandowski","raw_affiliation_strings":["The University of Manchester,Department of Electrical and Electronic Engineering,Manchester,UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester,Department of Electrical and Electronic Engineering,Manchester,UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076139003","display_name":"Piotr Dudek","orcid":"https://orcid.org/0000-0001-7934-556X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Piotr Dudek","raw_affiliation_strings":["The University of Manchester,Department of Electrical and Electronic Engineering,Manchester,UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester,Department of Electrical and Electronic Engineering,Manchester,UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5014928358"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24955409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.7810999751091003,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.7810999751091003,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11245","display_name":"Advanced Numerical Analysis Techniques","score":0.7644000053405762,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6912999749183655,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.8297662734985352},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7941347360610962},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6166737079620361},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.467976838350296},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43921807408332825},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36887162923812866},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10913032293319702}],"concepts":[{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.8297662734985352},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7941347360610962},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6166737079620361},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.467976838350296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43921807408332825},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36887162923812866},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10913032293319702},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas56072.2025.11044179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire/4581bd69-527e-4a43-a327-c079e69faa5e","is_oa":true,"landing_page_url":"https://research.manchester.ac.uk/en/publications/4581bd69-527e-4a43-a327-c079e69faa5e","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lewandowski, M & Dudek, P 2025, Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem. in 2025 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. https://doi.org/10.1109/ISCAS56072.2025.11044179","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"pmh:oai:pure.atira.dk:openaire/4581bd69-527e-4a43-a327-c079e69faa5e","is_oa":true,"landing_page_url":"https://research.manchester.ac.uk/en/publications/4581bd69-527e-4a43-a327-c079e69faa5e","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lewandowski, M & Dudek, P 2025, Design and FPGA Realization of QUBO hardware accelerator for MAX-CUT problem. in 2025 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. https://doi.org/10.1109/ISCAS56072.2025.11044179","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1208385249","https://openalex.org/W1509923235","https://openalex.org/W1974908481","https://openalex.org/W2005228957","https://openalex.org/W2024060531","https://openalex.org/W2034638017","https://openalex.org/W2039122980","https://openalex.org/W2077969951","https://openalex.org/W2095595785","https://openalex.org/W2122006505","https://openalex.org/W2197817604","https://openalex.org/W2578751696","https://openalex.org/W2734190907","https://openalex.org/W2887230019","https://openalex.org/W2921525502","https://openalex.org/W2984655992","https://openalex.org/W3013344182","https://openalex.org/W4225417080","https://openalex.org/W4285031017","https://openalex.org/W4293179730","https://openalex.org/W4386446786","https://openalex.org/W4409064026"],"related_works":["https://openalex.org/W2022544890","https://openalex.org/W2394097730","https://openalex.org/W2043523297","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Combinatorial":[0],"optimization":[1],"problems":[2],"are":[3,12],"fundamental":[4],"to":[5,20,51,75],"many":[6],"industrial":[7],"and":[8,17],"scientific":[9],"applications,":[10],"but":[11],"often":[13],"NP-hard,":[14],"requiring":[15],"heuristic":[16],"probabilistic":[18],"approaches":[19],"find":[21],"good":[22],"solutions":[23],"fast.":[24],"This":[25],"paper":[26],"presents":[27],"the":[28,33,76,82],"first":[29],"hardware":[30],"implementation":[31],"of":[32,69],"neuromorphic-inspired":[34],"NeuroSA":[35],"algorithm,":[36],"for":[37],"accelerating":[38],"Quadratic":[39],"Unconstrained":[40],"Binary":[41],"Optimization":[42],"(QUBO)":[43],"problems.":[44],"We":[45],"show":[46],"that":[47],"it":[48],"is":[49],"possible":[50],"run":[52],"a":[53,62,66],"standard":[54],"QUBO":[55],"benchmark":[56],"problem":[57],"with":[58,65],"800":[59],"variables":[60],"on":[61],"low-cost":[63],"FPGA":[64],"clock":[67],"speed":[68],"approximately":[70],"144":[71],"MHz,":[72],"which":[73],"converges":[74],"same":[77],"solution":[78],"value":[79],"found":[80],"by":[81],"numerical":[83],"solver.":[84]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
