{"id":"https://openalex.org/W4411725227","doi":"https://doi.org/10.1109/iscas56072.2025.11044103","title":"RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs","display_name":"RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725227","doi":"https://doi.org/10.1109/iscas56072.2025.11044103"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11044103","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013533880","display_name":"Varun Venkitaraman","orcid":"https://orcid.org/0000-0002-9871-0638"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Varun Venkitaraman","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000856914","display_name":"S. Bhargava","orcid":"https://orcid.org/0000-0003-3269-5348"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shrasti Bhargava","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114849334","display_name":"Tejeshwar Bhagatsing Thorawade","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tejeshwar B. Thorawade","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013020412","display_name":"Keerthi Sagar Kokkiligadda","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Kokkiligadda","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067689068","display_name":"Rahul Kumar","orcid":"https://orcid.org/0000-0001-6887-7106"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rahul Kumar","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5013533880"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18931795,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8691416382789612},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.7058091759681702},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.627717912197113},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5022351741790771},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4355434775352478}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8691416382789612},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.7058091759681702},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.627717912197113},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5022351741790771},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4355434775352478},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11044103","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1978659925","https://openalex.org/W1979527452","https://openalex.org/W2062189676","https://openalex.org/W2080592089","https://openalex.org/W2093036945","https://openalex.org/W2098701183","https://openalex.org/W2111804126","https://openalex.org/W2149234156","https://openalex.org/W2151233837","https://openalex.org/W2154396450","https://openalex.org/W2155893237","https://openalex.org/W2157134596","https://openalex.org/W2171164959","https://openalex.org/W2883073617","https://openalex.org/W2911669905","https://openalex.org/W3136405287","https://openalex.org/W4244814458","https://openalex.org/W4245105139","https://openalex.org/W4248800093","https://openalex.org/W4250981202","https://openalex.org/W4253046107","https://openalex.org/W4255387252","https://openalex.org/W4280604807","https://openalex.org/W6672328983","https://openalex.org/W6694513646","https://openalex.org/W6764609847"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2352941988"],"abstract_inverted_index":{"General-Purpose":[0],"GPUs":[1,40,56],"(GPGPUs)":[2],"are":[3],"ideal":[4],"for":[5,32],"parallel":[6],"processing":[7],"and":[8,50,89,119,152,166],"high":[9,77],"throughput.":[10],"However,":[11],"efficient":[12],"on-chip":[13],"memory":[14,34],"use":[15],"is":[16],"challenging":[17],"due":[18],"to":[19,26,98,115,134,147],"resource":[20],"conflicts":[21],"between":[22,117],"threads.":[23],"This":[24],"leads":[25],"sub-optimal":[27],"throughput,":[28],"highlighting":[29],"the":[30,58,139,150,164],"need":[31],"better":[33],"designs.":[35],"As":[36],"compute":[37],"demand":[38],"grows,":[39],"with":[41,76,125],"more":[42,82],"Streaming":[43],"Multiprocessors":[44],"(SMs)":[45],"emerge,":[46],"increasing":[47],"bandwidth":[48],"needs":[49],"intensifying":[51],"Network-on-Chip":[52],"(NoC)":[53],"traffic.":[54],"Current":[55],"partition":[57],"shared":[59,66,118],"Last-Level":[60],"Cache":[61],"(LLC)":[62],"into":[63],"uniform":[64],"slices":[65],"by":[67,145,161],"all":[68],"SMs.":[69],"While":[70],"this":[71],"reduces":[72,159],"miss":[73],"rates,":[74],"workloads":[75],"inter-SM":[78],"data":[79,100],"sharing":[80,101],"benefit":[81],"from":[83],"private":[84,120],"LLCs,":[85],"which":[86],"reduce":[87],"contention":[88],"improve":[90],"bandwidth.":[91],"We":[92],"propose":[93],"a":[94,110,126],"dynamic":[95],"profiling":[96],"method":[97],"evaluate":[99],"across":[102],"SMs":[103],"during":[104],"execution.":[105],"Using":[106],"this,":[107],"we":[108],"present":[109],"logistic":[111],"regression-based":[112],"decision":[113],"mechanism":[114],"switch":[116],"LLC":[121],"configurations":[122],"at":[123],"runtime,":[124],"twenty":[127],"five":[128],"thousand":[129],"cycle":[130],"reconfiguration":[131],"epoch":[132],"(compared":[133],"1":[135],"million":[136],"cycles":[137],"in":[138],"state-of-the-art).":[140],"Our":[141],"approach":[142],"boosts":[143],"performance":[144],"up":[146],"56%":[148],"over":[149,154,163,168],"baseline":[151,165],"29%":[153],"state-of-the-art":[155,169],"methods.":[156],"It":[157],"also":[158],"stalls":[160],"71%":[162],"59%":[167],"approach.":[170]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}