{"id":"https://openalex.org/W4411724962","doi":"https://doi.org/10.1109/iscas56072.2025.11044094","title":"Analysis of Non-Idealities in CMOS RX Front-End for Linear Phased Arrays","display_name":"Analysis of Non-Idealities in CMOS RX Front-End for Linear Phased Arrays","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411724962","doi":"https://doi.org/10.1109/iscas56072.2025.11044094"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11044094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026732812","display_name":"Francisco Aznar","orcid":"https://orcid.org/0000-0003-3629-0540"},"institutions":[{"id":"https://openalex.org/I4210100615","display_name":"Centro Universitario de la Defensa","ror":"https://ror.org/00nqz4988","country_code":"ES","type":"education","lineage":["https://openalex.org/I4210100615"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Francisco Aznar","raw_affiliation_strings":["Centro Universitario De La Defensa,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain"],"affiliations":[{"raw_affiliation_string":"Centro Universitario De La Defensa,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain","institution_ids":["https://openalex.org/I4210100615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114592651","display_name":"Uxua Esteban-Eraso","orcid":null},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Uxua Esteban-Eraso","raw_affiliation_strings":["Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072417648","display_name":"Antonio D. Mart\u00ednez-P\u00e9rez","orcid":"https://orcid.org/0000-0001-5402-1251"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio D. Mart\u00ednez-P\u00e9rez","raw_affiliation_strings":["Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087490497","display_name":"Carlos S\u00e1nchez\u2010Azqueta","orcid":"https://orcid.org/0000-0002-8236-825X"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"C. S\u00e1nchez-Azqueta","raw_affiliation_strings":["Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075718351","display_name":"S. Celma","orcid":"https://orcid.org/0000-0003-0182-7723"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Santiago Celma","raw_affiliation_strings":["Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad de Zaragoza,Group of Electronic Design (GDE) - Aragon Institute for Engineering Research (I3A),Zaragoza,Spain","institution_ids":["https://openalex.org/I255234318"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5026732812"],"corresponding_institution_ids":["https://openalex.org/I4210100615"],"apc_list":null,"apc_paid":null,"fwci":3.4842,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.92719359,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11946","display_name":"Antenna Design and Optimization","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11946","display_name":"Antenna Design and Optimization","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.6536418199539185},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6432366967201233},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40819406509399414},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3916454017162323},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3162837028503418},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.10450851917266846}],"concepts":[{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.6536418199539185},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6432366967201233},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40819406509399414},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3916454017162323},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3162837028503418},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.10450851917266846}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11044094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11044094","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W635276851","https://openalex.org/W2011901342","https://openalex.org/W2158017712","https://openalex.org/W3081758246","https://openalex.org/W4212835537","https://openalex.org/W4249074589","https://openalex.org/W4382727560","https://openalex.org/W4404238727"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W2617868873","https://openalex.org/W2109445684","https://openalex.org/W2081082331"],"abstract_inverted_index":{"This":[0],"paper":[1],"analyses":[2],"the":[3,48,57,70,83,86],"phase":[4,34,58],"performance":[5],"of":[6,31,47,77],"a":[7,13,80],"RX":[8],"front-end":[9,25,71],"architecture":[10],"implemented":[11],"in":[12,40,75],"65-nm":[14],"CMOS":[15],"process":[16],"for":[17],"linear":[18],"phased":[19],"arrays":[20],"at":[21],"24":[22],"GHz.":[23],"The":[24,45],"is":[26],"based":[27],"on":[28],"an":[29],"array":[30],"LNAs":[32],"and":[33,42,62],"shifters,":[35],"which":[36],"can":[37],"be":[38],"used":[39],"analog":[41],"hybrid":[43],"beamformers.":[44],"penalties":[46],"radiation":[49],"pattern":[50],"are":[51],"associated":[52],"with":[53],"metrics":[54],"calculated":[55],"from":[56],"performance.":[59],"PVT":[60,78],"variations":[61],"mismatch":[63],"have":[64],"been":[65],"included.":[66],"Results":[67],"show":[68],"that":[69],"could":[72],"potentially":[73],"attain,":[74],"spite":[76],"variations,":[79],"value":[81],"near":[82],"defined":[84],"by":[85],"mismatch.":[87]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
