{"id":"https://openalex.org/W4411724932","doi":"https://doi.org/10.1109/iscas56072.2025.11043825","title":"A 4kb 4T eDRAM with Balanced Retention Time Adjustment","display_name":"A 4kb 4T eDRAM with Balanced Retention Time Adjustment","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411724932","doi":"https://doi.org/10.1109/iscas56072.2025.11043825"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111272095","display_name":"Sayan Kumar","orcid":"https://orcid.org/0009-0004-7895-9534"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Sayan Kumar","raw_affiliation_strings":["University College Dublin,School of Electric and Electronic Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin,School of Electric and Electronic Engineering","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007581748","display_name":"Dennis Andrade\u2010Miceli","orcid":"https://orcid.org/0000-0002-1351-2748"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Dennis Andrade-Miceli","raw_affiliation_strings":["University College Dublin,School of Electric and Electronic Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin,School of Electric and Electronic Engineering","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5118663985","display_name":"Chawin Khongprasongsiri","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Chawin Khongprasongsiri","raw_affiliation_strings":["University College Dublin,School of Electric and Electronic Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin,School of Electric and Electronic Engineering","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050565374","display_name":"Teerachot Siriburanon","orcid":"https://orcid.org/0000-0003-1658-9596"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Teerachot Siriburanon","raw_affiliation_strings":["University College Dublin,School of Electric and Electronic Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin,School of Electric and Electronic Engineering","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027017637","display_name":"Robert Bogdan Staszewski","orcid":"https://orcid.org/0000-0001-9848-1129"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"R. Bogdan Staszewski","raw_affiliation_strings":["University College Dublin,School of Electric and Electronic Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin,School of Electric and Electronic Engineering","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I100930933"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9750000238418579,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9746999740600586,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5496287941932678},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5487292408943176},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4219121038913727},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3864724040031433},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35303884744644165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3250393867492676},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.320737361907959},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1987360715866089},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16718173027038574},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.12618213891983032}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5496287941932678},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5487292408943176},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4219121038913727},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3864724040031433},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35303884744644165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3250393867492676},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.320737361907959},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1987360715866089},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16718173027038574},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.12618213891983032}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320847","display_name":"Science Foundation Ireland","ror":"https://ror.org/0271asj38"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2116567461"],"related_works":["https://openalex.org/W2143400404","https://openalex.org/W2801267388","https://openalex.org/W759091488","https://openalex.org/W2141872534","https://openalex.org/W2110321764","https://openalex.org/W2004082605","https://openalex.org/W4362604459","https://openalex.org/W3097818333","https://openalex.org/W1530056031","https://openalex.org/W2074922484"],"abstract_inverted_index":{"Gain-cell":[0],"(GC)":[1],"based":[2],"eDRAM":[3,25,128],"has":[4],"been":[5],"a":[6,28,123],"promising":[7],"memory":[8,87,129],"topology":[9,88],"due":[10,53],"to":[11,54,94],"the":[12,24,37,50,55,61,73,95,100,111,119,149,159,174,180,186],"lower":[13,172],"area":[14,92],"footprint":[15],"and":[16,43,98,107,134,139],"energy":[17],"consumption":[18,142],"than":[19,173,185],"its":[20],"SRAM":[21,177],"counterpart.":[22],"However,":[23],"suffers":[26],"from":[27],"short":[29],"retention":[30,38,62,75,101,150],"time":[31,39,63,102,151],"in":[32,115,179],"finer":[33],"technology":[34],"nodes.":[35],"Enhancing":[36],"requires":[40],"both":[41],"pMOS":[42],"nMOS":[44],"devices,":[45],"but":[46],"this":[47],"inadvertently":[48],"increases":[49],"cell":[51],"size":[52],"minimum":[56],"spacing":[57],"between":[58],"them.":[59],"Further,":[60],"is":[64,170],"dominated":[65],"by":[66,103],"either":[67],"logic":[68,105,160],"\u20181\u2019":[69,108],"or":[70],"\u20180\u2019,":[71],"lowering":[72],"overall":[74],"time.":[76],"In":[77],"our":[78],"work,":[79],"we":[80],"propose":[81],"an":[82,91],"nMOS-only":[83],"GC-based":[84],"4T":[85,156],"GC-eDRAM":[86,97],"that":[89],"occupies":[90,164],"comparable":[93],"3T":[96],"enhances":[99],"balancing":[104],"\u20180\u2019":[106],"via":[109],"controlling":[110],"leakage":[112],"path.":[113],"Designed":[114],"GlobalFoundries":[116],"22-nm":[117],"FD-SOI,":[118],"post-layout":[120],"simulation":[121],"of":[122,137,152],"dual":[124],"port":[125],"128\u00d7128":[126],"(4kb)":[127],"array":[130],"shows":[131],"610":[132],"\u03bcW":[133,136],"490":[135],"write":[138],"read":[140],"power":[141],"at":[143],"250":[144],"MHz,":[145],"respectively,":[146],"while":[147,182],"maintaining":[148],"25":[153],"\u03bcs.":[154],"The":[155],"bit-cell":[157],"with":[158],"design":[161],"rule":[162],"only":[163],"0.12":[165],"\u03bcm<sup":[166],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[167],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>,":[168],"which":[169],"1.5\u00d7":[171],"two-port":[175],"8T":[176],"cells":[178],"PDK,":[181],"1.1\u00d7":[183],"larger":[184],"single-port":[187],"6T":[188],"SRAM.":[189]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}