{"id":"https://openalex.org/W4411725706","doi":"https://doi.org/10.1109/iscas56072.2025.11043743","title":"Multi-Level Analog Computing-In-Memory FeFET-based Unit Cell for Deep Learning","display_name":"Multi-Level Analog Computing-In-Memory FeFET-based Unit Cell for Deep Learning","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725706","doi":"https://doi.org/10.1109/iscas56072.2025.11043743"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043743","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043743","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063297299","display_name":"\u00d3. Pereira-Rial","orcid":"https://orcid.org/0000-0001-9021-9273"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"\u00d3. Pereira-Rial","raw_affiliation_strings":["Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain"],"affiliations":[{"raw_affiliation_string":"Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048396671","display_name":"Hannes Dahlberg","orcid":"https://orcid.org/0000-0002-6787-3346"},"institutions":[{"id":"https://openalex.org/I187531555","display_name":"Lund University","ror":"https://ror.org/012a77v79","country_code":"SE","type":"education","lineage":["https://openalex.org/I187531555"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Hannes Dahlberg","raw_affiliation_strings":["Lund University,Electromagnetics and Nanoelectronics,Department of Electrical and Information Technology,Lund,Sweden"],"affiliations":[{"raw_affiliation_string":"Lund University,Electromagnetics and Nanoelectronics,Department of Electrical and Information Technology,Lund,Sweden","institution_ids":["https://openalex.org/I187531555"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025364375","display_name":"D. Garc\u00eda-Lesta","orcid":"https://orcid.org/0000-0002-9895-9839"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"D. Garc\u00eda-Lesta","raw_affiliation_strings":["Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain"],"affiliations":[{"raw_affiliation_string":"Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077550469","display_name":"V.M. Brea","orcid":"https://orcid.org/0000-0003-0078-0425"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"V.M. Brea","raw_affiliation_strings":["Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain"],"affiliations":[{"raw_affiliation_string":"Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006623829","display_name":"Pablo L\u00f3pez","orcid":"https://orcid.org/0000-0001-5424-3006"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"P. L\u00f3pez","raw_affiliation_strings":["Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain"],"affiliations":[{"raw_affiliation_string":"Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041970396","display_name":"D. Cabello","orcid":"https://orcid.org/0000-0002-4859-2899"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"D. Cabello","raw_affiliation_strings":["Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain"],"affiliations":[{"raw_affiliation_string":"Universidade de Santiago de Compostela,Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS),Santiago de Compostela,Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007984578","display_name":"Lars\u2010Erik Wernersson","orcid":"https://orcid.org/0000-0002-1039-5849"},"institutions":[{"id":"https://openalex.org/I187531555","display_name":"Lund University","ror":"https://ror.org/012a77v79","country_code":"SE","type":"education","lineage":["https://openalex.org/I187531555"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Lars-Erik Wernersson","raw_affiliation_strings":["Lund University,Electromagnetics and Nanoelectronics,Department of Electrical and Information Technology,Lund,Sweden"],"affiliations":[{"raw_affiliation_string":"Lund University,Electromagnetics and Nanoelectronics,Department of Electrical and Information Technology,Lund,Sweden","institution_ids":["https://openalex.org/I187531555"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5063297299"],"corresponding_institution_ids":["https://openalex.org/I200284239"],"apc_list":null,"apc_paid":null,"fwci":0.67,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.71800517,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6896563768386841},{"id":"https://openalex.org/keywords/analog-computer","display_name":"Analog computer","score":0.48186835646629333},{"id":"https://openalex.org/keywords/unit","display_name":"Unit (ring theory)","score":0.45714643597602844},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4466545283794403},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1539297103881836},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13716456294059753},{"id":"https://openalex.org/keywords/psychology","display_name":"Psychology","score":0.08119621872901917}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6896563768386841},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.48186835646629333},{"id":"https://openalex.org/C122637931","wikidata":"https://www.wikidata.org/wiki/Q118084","display_name":"Unit (ring theory)","level":2,"score":0.45714643597602844},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4466545283794403},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1539297103881836},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13716456294059753},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.08119621872901917},{"id":"https://openalex.org/C145420912","wikidata":"https://www.wikidata.org/wiki/Q853077","display_name":"Mathematics education","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043743","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043743","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:lup.lub.lu.se:2a00a4e2-9c7e-4d24-8d2f-bb63dcae1e9c","is_oa":false,"landing_page_url":"https://lup.lub.lu.se/record/2a00a4e2-9c7e-4d24-8d2f-bb63dcae1e9c","pdf_url":null,"source":{"id":"https://openalex.org/S4306400536","display_name":"Lund University Publications (Lund University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I187531555","host_organization_name":"Lund University","host_organization_lineage":["https://openalex.org/I187531555"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN: 0271-4310","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320326655","display_name":"Xunta de Galicia","ror":"https://ror.org/0181xnw06"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2487018225","https://openalex.org/W2568885332","https://openalex.org/W2769364246","https://openalex.org/W3013705992","https://openalex.org/W3136117125","https://openalex.org/W3166948729","https://openalex.org/W3186271703","https://openalex.org/W4293182211","https://openalex.org/W4294891560","https://openalex.org/W4312958753","https://openalex.org/W4316661092","https://openalex.org/W4387492098","https://openalex.org/W4388286156"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"This":[0],"paper":[1],"shows":[2],"a":[3,25,45,73,87,109,131],"FeFET-based":[4,18],"analog":[5],"multi-level":[6],"unit":[7,19,41],"cell":[8,20,42,133],"for":[9,12,79],"computing-in-memory":[10],"applications":[11],"Deep":[13],"Neural":[14],"Networks":[15],"(DNN).":[16],"The":[17,40],"performs":[21],"input-weight":[22],"multiplication":[23],"with":[24,44,108,134],"Back-End-Of-Line":[26],"(BEOL)":[27],"ferro-electric":[28],"HZO":[29],"FeFET":[30,52,120],"device":[31,53],"on":[32,72],"top":[33],"of":[34,102,118,136,141],"standard":[35],"180":[36],"nm":[37],"CMOS":[38,58],"circuits.":[39],"works":[43],"feedback":[46,76,127],"mechanism":[47,77],"which":[48],"combines":[49],"an":[50],"in-house":[51],"to":[54,61,67,85,130,139],"store":[55],"weights":[56],"and":[57,82],"transistors":[59],"underneath":[60],"provide":[62],"outputs":[63],"in":[64,96],"current":[65],"mode":[66],"be":[68],"integrated":[69],"over":[70],"time":[71,90],"capacitor.":[74],"Said":[75],"compensates":[78],"device-to-device":[80],"variability,":[81],"would":[83],"permit":[84],"calibrate":[86],"system":[88],"against":[89],"variations,":[91],"something":[92],"not":[93],"usually":[94],"included":[95],"cross-bar":[97],"solutions.":[98,143],"Joint":[99],"electrical":[100],"simulations":[101,123],"the":[103,115,119],"FeFET-CMOS":[104],"circuit":[105],"are":[106],"performed":[107],"compact":[110],"Verilog-A":[111],"model":[112],"extracted":[113],"from":[114],"experimental":[116],"characterization":[117],"devices.":[121],"Electrical":[122],"show":[124],"that":[125,140],"our":[126],"approach":[128],"leads":[129],"multi-bit":[132],"5-bits":[135],"resolution,":[137],"superior":[138],"state-of-the-art":[142]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-19T08:26:33.389920","created_date":"2025-10-10T00:00:00"}