{"id":"https://openalex.org/W4411725090","doi":"https://doi.org/10.1109/iscas56072.2025.11043729","title":"A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm","display_name":"A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725090","doi":"https://doi.org/10.1109/iscas56072.2025.11043729"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5118664006","display_name":"Stefano Bonomi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Stefano Bonomi","raw_affiliation_strings":["Infineon Technologies AG,Villach,Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Villach,Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061164775","display_name":"Werner Grollitsch","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Werner Grollitsch","raw_affiliation_strings":["Infineon Technologies AG,Villach,Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Villach,Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031192574","display_name":"Sie Boo Chiang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144507","display_name":"Infineon Technologies (Singapore)","ror":"https://ror.org/0470e9841","country_code":"SG","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210144507"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Sie Boo Chiang","raw_affiliation_strings":["Infineon Technologies AG,Singapore,Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Singapore,Singapore","institution_ids":["https://openalex.org/I4210144507"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011833987","display_name":"Roberto Nonis","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Roberto Nonis","raw_affiliation_strings":["Infineon Technologies AG,Villach,Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Villach,Austria","institution_ids":["https://openalex.org/I4210131793"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14811665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9793999791145325,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9767000079154968,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dropout","display_name":"Dropout (neural networks)","score":0.8111642599105835},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6387734413146973},{"id":"https://openalex.org/keywords/power-supply-rejection-ratio","display_name":"Power supply rejection ratio","score":0.5834246873855591},{"id":"https://openalex.org/keywords/regulator","display_name":"Regulator","score":0.5066848397254944},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48247864842414856},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42050081491470337},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21523669362068176}],"concepts":[{"id":"https://openalex.org/C2776145597","wikidata":"https://www.wikidata.org/wiki/Q25339462","display_name":"Dropout (neural networks)","level":2,"score":0.8111642599105835},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6387734413146973},{"id":"https://openalex.org/C15892472","wikidata":"https://www.wikidata.org/wiki/Q1482413","display_name":"Power supply rejection ratio","level":4,"score":0.5834246873855591},{"id":"https://openalex.org/C6929976","wikidata":"https://www.wikidata.org/wiki/Q3771881","display_name":"Regulator","level":3,"score":0.5066848397254944},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48247864842414856},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42050081491470337},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21523669362068176},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7699999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2094282675","https://openalex.org/W2789664164","https://openalex.org/W2894668784","https://openalex.org/W2921226981","https://openalex.org/W3005240242","https://openalex.org/W3046131452","https://openalex.org/W4206179076","https://openalex.org/W4286571902","https://openalex.org/W4391092546","https://openalex.org/W4392746169","https://openalex.org/W4400233668"],"related_works":["https://openalex.org/W3082178636","https://openalex.org/W2055315449","https://openalex.org/W2354064740","https://openalex.org/W2884961406","https://openalex.org/W2359236028","https://openalex.org/W2389923937","https://openalex.org/W2782041652","https://openalex.org/W2612657834","https://openalex.org/W2109445684","https://openalex.org/W2081082331"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,37,45,56,74],"novel":[4],"digital":[5],"voltage":[6,57],"regulator":[7,30,69],"architecture":[8,14],"for":[9],"System-on-Chip":[10],"(SoC)":[11],"applications.":[12],"The":[13,68],"includes":[15],"an":[16,32,93],"Analog":[17,63,121],"Nested":[18,64,122],"Loop,":[19],"which":[20],"improves":[21,104,114],"the":[22,29,62,80,99,111,120],"regulator's":[23],"performance.":[24],"Implemented":[25],"in":[26],"28nm":[27],"technology,":[28],"occupies":[31],"area":[33],"of":[34,40,51,59],"0.011mm2and":[35],"has":[36],"total":[38],"capacitance":[39],"10.6pF.":[41],"Measurement":[42],"results":[43],"show":[44],"Power":[46],"Supply":[47],"Rejection":[48],"Ratio":[49],"(PSRR)":[50],"-44dB":[52],"at":[53,102],"1MHz":[54],"and":[55,79,85,110],"ripple":[58],"3.61mVpp":[60],"when":[61,119],"Loop":[65,76,123],"is":[66,70,124],"enabled.":[67,125],"also":[71],"tested":[72],"with":[73,92],"Phase-Locked":[75],"(PLL)":[77],"oscillator,":[78],"resulting":[81],"PLL":[82],"Phase":[83,100],"Noise":[84,101],"Jitter":[86,113],"are":[87],"compared":[88],"to":[89,108,117],"those":[90],"obtained":[91],"external,":[94],"clean":[95],"supply":[96],"source.":[97],"Specifically,":[98],"100kHz":[103],"from":[105,115],"-":[106],"96dBc/Hz":[107],"-97.5dBc/Hz,":[109],"absolute":[112],"97psrms":[116],"95psrms,":[118]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
