{"id":"https://openalex.org/W4411726705","doi":"https://doi.org/10.1109/iscas56072.2025.11043686","title":"A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs","display_name":"A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411726705","doi":"https://doi.org/10.1109/iscas56072.2025.11043686"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043686","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012420168","display_name":"Andrea Galimberti","orcid":"https://orcid.org/0000-0003-0254-3933"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Galimberti","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056381758","display_name":"Gabriele Montanaro","orcid":"https://orcid.org/0000-0003-1119-2629"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gabriele Montanaro","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Andrea Motta","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Motta","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5116054348","display_name":"Federico Proverbio","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Federico Proverbio","raw_affiliation_strings":["E4 Computer Engineering,Scandiano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"E4 Computer Engineering,Scandiano,Italy","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016373122","display_name":"Davide Zoni","orcid":"https://orcid.org/0000-0002-9951-062X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Zoni","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB), Politecnico di Milano,Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.2134,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.95139807,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9617000222206116,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9617000222206116,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9603999853134155,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmarking","display_name":"Benchmarking","score":0.8851083517074585},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7312045693397522},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.634392499923706},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.629730761051178},{"id":"https://openalex.org/keywords/data-center","display_name":"Data center","score":0.539027750492096},{"id":"https://openalex.org/keywords/center","display_name":"Center (category theory)","score":0.516140341758728},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4808695912361145},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44713330268859863},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35175198316574097},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11831662058830261},{"id":"https://openalex.org/keywords/business","display_name":"Business","score":0.07644805312156677}],"concepts":[{"id":"https://openalex.org/C86251818","wikidata":"https://www.wikidata.org/wiki/Q816754","display_name":"Benchmarking","level":2,"score":0.8851083517074585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7312045693397522},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.634392499923706},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.629730761051178},{"id":"https://openalex.org/C153740404","wikidata":"https://www.wikidata.org/wiki/Q671224","display_name":"Data center","level":2,"score":0.539027750492096},{"id":"https://openalex.org/C2779463800","wikidata":"https://www.wikidata.org/wiki/Q5062222","display_name":"Center (category theory)","level":2,"score":0.516140341758728},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4808695912361145},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44713330268859863},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35175198316574097},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11831662058830261},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.07644805312156677},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C8010536","wikidata":"https://www.wikidata.org/wiki/Q160398","display_name":"Crystallography","level":1,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043686","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1293270","is_oa":false,"landing_page_url":"https://hdl.handle.net/11311/1293270","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2024277001","https://openalex.org/W2442049994","https://openalex.org/W2800690434","https://openalex.org/W2914297410","https://openalex.org/W2939057911","https://openalex.org/W3034977853","https://openalex.org/W3132370594","https://openalex.org/W3158338328","https://openalex.org/W4245276998","https://openalex.org/W4366274287","https://openalex.org/W4379033852","https://openalex.org/W4381798742","https://openalex.org/W4390693436","https://openalex.org/W4404789045","https://openalex.org/W4406014479"],"related_works":["https://openalex.org/W4238897586","https://openalex.org/W435179959","https://openalex.org/W2619091065","https://openalex.org/W2059640416","https://openalex.org/W1490753184","https://openalex.org/W2379482911","https://openalex.org/W2645858920","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"FPGAs":[0,35],"are":[1],"increasingly":[2],"utilized":[3],"in":[4,14,50],"data":[5,86,106],"centers":[6],"due":[7],"to":[8,11,31,79,101,111,121],"their":[9],"ability":[10],"exploit":[12],"parallelism":[13],"computationally":[15],"intensive":[16],"workloads.":[17],"Modern":[18],"workloads":[19],"demand":[20],"the":[21,76,93,117],"transfer":[22],"of":[23,26],"vast":[24],"amounts":[25],"information,":[27],"making":[28],"it":[29],"essential":[30],"optimize":[32],"communication":[33],"between":[34],"and":[36,70,84],"memory.":[37],"This":[38],"paper":[39],"introduces":[40],"a":[41],"novel":[42],"benchmarking":[43],"platform":[44],"for":[45],"evaluating":[46],"DDR4":[47,124],"memory":[48,63,82,103,128],"performance":[49,125],"data-center-class":[51],"FPGAs.":[52],"The":[53,114],"proposed":[54],"solution":[55],"features":[56],"highly":[57],"configurable":[58],"traffic":[59,129],"generation":[60],"with":[61,105],"complex":[62],"access":[64],"patterns":[65],"defined":[66],"at":[67],"run":[68],"time":[69],"can":[71],"be":[72],"flexibly":[73],"instantiated":[74],"on":[75],"target":[77],"FPGA":[78],"support":[80],"multiple":[81],"channels":[83,104],"varying":[85],"rates.":[87],"An":[88],"extensive":[89],"experimental":[90],"campaign":[91],"targets":[92],"AMD":[94],"Kintex":[95],"UltraScale":[96],"115":[97],"FPGA,":[98],"encompassing":[99],"up":[100],"three":[102],"rates":[107],"ranging":[108],"from":[109],"1600":[110],"2400":[112],"MT/s.":[113],"results":[115],"demonstrate":[116],"benchmaking":[118],"platform\u2019s":[119],"capability":[120],"effectively":[122],"evaluate":[123],"across":[126],"various":[127],"configurations.":[130]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}