{"id":"https://openalex.org/W4411725504","doi":"https://doi.org/10.1109/iscas56072.2025.11043419","title":"Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery","display_name":"Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725504","doi":"https://doi.org/10.1109/iscas56072.2025.11043419"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043419","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043419","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102873970","display_name":"Xu Luo","orcid":"https://orcid.org/0000-0001-6942-896X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Luo","raw_affiliation_strings":["Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005420474","display_name":"Yuanyuan Han","orcid":"https://orcid.org/0000-0001-7043-5390"},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuanyuan Han","raw_affiliation_strings":["Zhangjiang Laboratory,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory,Shanghai,China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075507579","display_name":"Xu Cheng","orcid":"https://orcid.org/0000-0002-0314-0178"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Cheng","raw_affiliation_strings":["Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100656792","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University,State key Laboratory of Integrated Chips and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14869654,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.7988975644111633},{"id":"https://openalex.org/keywords/interlocking","display_name":"Interlocking","score":0.7931466102600098},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7582245469093323},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.7236113548278809},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6550809144973755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6270996928215027},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.5760762095451355},{"id":"https://openalex.org/keywords/isolation","display_name":"Isolation (microbiology)","score":0.48564210534095764},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38155168294906616},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3471706509590149},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2228938639163971},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12457874417304993},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09850099682807922},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08696067333221436},{"id":"https://openalex.org/keywords/structural-engineering","display_name":"Structural engineering","score":0.06908205151557922},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.06129443645477295}],"concepts":[{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.7988975644111633},{"id":"https://openalex.org/C2778844933","wikidata":"https://www.wikidata.org/wiki/Q630950","display_name":"Interlocking","level":2,"score":0.7931466102600098},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7582245469093323},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.7236113548278809},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6550809144973755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6270996928215027},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.5760762095451355},{"id":"https://openalex.org/C2775941552","wikidata":"https://www.wikidata.org/wiki/Q25212305","display_name":"Isolation (microbiology)","level":2,"score":0.48564210534095764},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38155168294906616},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3471706509590149},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2228938639163971},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12457874417304993},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09850099682807922},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08696067333221436},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.06908205151557922},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.06129443645477295},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C89423630","wikidata":"https://www.wikidata.org/wiki/Q7193","display_name":"Microbiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043419","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043419","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1981970801","https://openalex.org/W2002612140","https://openalex.org/W2050431855","https://openalex.org/W2141658437","https://openalex.org/W2153751624","https://openalex.org/W2160778748","https://openalex.org/W2161549238","https://openalex.org/W2907583718","https://openalex.org/W3081672332","https://openalex.org/W3155037334","https://openalex.org/W3162523375","https://openalex.org/W3191703988","https://openalex.org/W4221121827","https://openalex.org/W4388505092"],"related_works":["https://openalex.org/W4290647047","https://openalex.org/W2066033226","https://openalex.org/W2363504003","https://openalex.org/W2548582980","https://openalex.org/W2620706469","https://openalex.org/W2052914698","https://openalex.org/W2088929465","https://openalex.org/W2612883256","https://openalex.org/W4386933833","https://openalex.org/W1030007664"],"abstract_inverted_index":{"SRAM":[0,26],"suffers":[1],"from":[2,106],"single":[3,8,40],"event":[4,9],"upset":[5,42,52],"(SEU)":[6],"and":[7,48,121],"transient":[10],"(SET)":[11],"in":[12,73,77],"harsh":[13],"radiation":[14],"environments.":[15],"In":[16],"this":[17,84],"paper,":[18],"a":[19],"Penta":[20],"Interlocking":[21],"Dual":[22],"Ports":[23],"14T":[24],"(PIDP-14T)":[25],"cell":[27,32,103,125],"is":[28,114],"proposed":[29],"to":[30,67,94,133],"improve":[31],"stability.":[33],"The":[34,97],"PIDP-14T":[35],"has":[36],"the":[37,61,81,102,111,122],"immunity":[38],"of":[39,63,109,118],"node":[41,45,51],"(SNU),":[43],"multiple":[44],"upsets":[46],"(MNU)":[47],"specific":[49],"triple":[50],"(TNU).":[53],"An":[54],"inside-bit":[55],"interleaving":[56],"layout":[57],"isolation":[58],"method":[59],"increases":[60],"distance":[62],"nearest":[64],"sensitive":[65],"nodes":[66],"2.409":[68],"\u00b5m.":[69],"Additionally,":[70],"as":[71],"SET":[72],"peripheral":[74],"circuit":[75,93],"results":[76,99],"half-select":[78],"disturbance":[79,135],"during":[80],"operation":[82],"cycle,":[83],"paper":[85],"introduced":[86],"double":[87],"module":[88],"redundant":[89],"(DMR)":[90],"hardened":[91,128],"decoding":[92,129],"remove":[95],"SET.":[96,138],"simulation":[98],"show":[100],"that":[101],"can":[104],"recover":[105],"special":[107],"MNU":[108],"which":[110],"critical":[112],"charge":[113],"almost":[115],"4":[116],"times":[117],"other":[119],"cells,":[120],"dual":[123],"gate":[124],"with":[126],"DMR":[127],"array":[130],"are":[131],"robust":[132],"write":[134],"caused":[136],"by":[137]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}