{"id":"https://openalex.org/W4411726101","doi":"https://doi.org/10.1109/iscas56072.2025.11043294","title":"A Resource-efficient Dually-addressable Memory Architecture on FPGA","display_name":"A Resource-efficient Dually-addressable Memory Architecture on FPGA","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411726101","doi":"https://doi.org/10.1109/iscas56072.2025.11043294"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043294","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043294","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100827133","display_name":"Yanjun Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Yanjun Yang","raw_affiliation_strings":["The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015343376","display_name":"Christos Giotis","orcid":"https://orcid.org/0000-0002-2002-2237"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Christos Giotis","raw_affiliation_strings":["The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088089733","display_name":"Themis Prodromakis","orcid":"https://orcid.org/0000-0002-6267-6909"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Themis Prodromakis","raw_affiliation_strings":["The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":null,"display_name":"Alex Serb","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alex Serb","raw_affiliation_strings":["The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,Centre for Electronics Frontiers, School of Engineering,Edinburgh,The United Kingdom","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100827133"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":2.3189,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.86508603,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7510272264480591},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6944168210029602},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6895257234573364},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6264257431030273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49718907475471497},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.4835381507873535},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33862197399139404},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.129093736410141}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7510272264480591},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6944168210029602},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6895257234573364},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6264257431030273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49718907475471497},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.4835381507873535},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33862197399139404},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.129093736410141},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043294","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043294","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1536792390","https://openalex.org/W2006115588","https://openalex.org/W2013406643","https://openalex.org/W2062143991","https://openalex.org/W2068933159","https://openalex.org/W2091830734","https://openalex.org/W2231737954","https://openalex.org/W2561621772","https://openalex.org/W2605142259","https://openalex.org/W2760769382","https://openalex.org/W2786330586","https://openalex.org/W2929407385","https://openalex.org/W2947178375","https://openalex.org/W2982036057","https://openalex.org/W3159859185","https://openalex.org/W3205734318","https://openalex.org/W4239721110","https://openalex.org/W4385187186","https://openalex.org/W4386609390","https://openalex.org/W4388084663","https://openalex.org/W4402216611","https://openalex.org/W6631527096"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2316202402","https://openalex.org/W2074043759","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2038503502"],"abstract_inverted_index":{"To":[0],"address":[1],"memory":[2],"throughput":[3],"challenges":[4],"in":[5],"contemporary":[6],"computing":[7],"systems,":[8],"content-addressable":[9],"memories":[10,14],"(CAMs)":[11],"and":[12,75],"dually-addressable":[13],"(DAMs)":[15],"are":[16],"implemented":[17,65],"to":[18,49,82],"enable":[19,50],"fast":[20],"search":[21],"operations.":[22],"However,":[23],"current":[24],"FPGA":[25,48,69],"implementations":[26],"severely":[27],"lack":[28],"dual":[29],"addressability":[30],"with":[31,70],"high":[32],"resource":[33],"costs.":[34],"In":[35],"this":[36],"paper,":[37],"we":[38],"present":[39],"a":[40,79],"resource-efficient":[41],"Block":[42],"RAM":[43],"(BRAM)-based":[44],"DAM":[45,83],"architecture":[46],"on":[47,66],"effective":[51],"database":[52],"manipulations":[53],"without":[54],"data":[55],"duplication.":[56],"An":[57],"example":[58],"design":[59],"of":[60],"size":[61],"8\u00d7512\u00d736":[62],"bits":[63],"is":[64],"Xilinx":[67],"Virtex-7":[68],"4":[71],"BRAM36,":[72],"683":[73],"LUTs,":[74],"248":[76],"FFs,":[77],"reaching":[78],"100%":[80],"BRAM":[81],"efficiency.":[84]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}