{"id":"https://openalex.org/W4411727111","doi":"https://doi.org/10.1109/iscas56072.2025.11043266","title":"Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing","display_name":"Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411727111","doi":"https://doi.org/10.1109/iscas56072.2025.11043266"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010602715","display_name":"Yu-Cheng Lu","orcid":"https://orcid.org/0009-0007-4845-6647"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Cheng Lu","raw_affiliation_strings":["National Taiwan University,Graduate School of Advanced Technology,Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate School of Advanced Technology,Taipei,Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016863989","display_name":"Meng-Lin Wu","orcid":"https://orcid.org/0000-0001-9990-8710"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Meng-Lin Wu","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering,Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering,Taipei,Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083596674","display_name":"Vita Pi\u2010Ho Hu","orcid":"https://orcid.org/0000-0002-6216-214X"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Vita Pi-Ho Hu","raw_affiliation_strings":["National Taiwan University,Graduate School of Advanced Technology,Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate School of Advanced Technology,Taipei,Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5010602715"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":4.3478,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.93724195,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6072258353233337},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6054434776306152},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.523202657699585},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.519612729549408},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.48374414443969727},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.47274741530418396},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4405444860458374},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3373048007488251},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2344152331352234},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2221933901309967},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.19405993819236755},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15703481435775757},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.12189406156539917}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6072258353233337},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6054434776306152},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.523202657699585},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.519612729549408},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.48374414443969727},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.47274741530418396},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4405444860458374},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3373048007488251},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2344152331352234},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2221933901309967},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.19405993819236755},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15703481435775757},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.12189406156539917},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7099999785423279}],"awards":[],"funders":[{"id":"https://openalex.org/F4320331164","display_name":"National Science and Technology Council","ror":"https://ror.org/00wnb9798"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W2605777874","https://openalex.org/W2927608144","https://openalex.org/W3006006803","https://openalex.org/W3082732228","https://openalex.org/W3110197395","https://openalex.org/W3136593877","https://openalex.org/W3159537059","https://openalex.org/W3196215375","https://openalex.org/W3211992815","https://openalex.org/W4200093542","https://openalex.org/W4226248601","https://openalex.org/W4226393975","https://openalex.org/W4285244365","https://openalex.org/W4286571677","https://openalex.org/W4286571731","https://openalex.org/W4286571859","https://openalex.org/W4308471346","https://openalex.org/W4313203552","https://openalex.org/W4317496701","https://openalex.org/W4317793552","https://openalex.org/W4378805922","https://openalex.org/W4383503912","https://openalex.org/W4385192418","https://openalex.org/W4385215863","https://openalex.org/W4385217824","https://openalex.org/W4386124236","https://openalex.org/W4387872739","https://openalex.org/W4389389310","https://openalex.org/W4391594505","https://openalex.org/W4399154615","https://openalex.org/W4399893246","https://openalex.org/W4400230042","https://openalex.org/W4401879634","https://openalex.org/W4401880245","https://openalex.org/W4401880564","https://openalex.org/W4407693233"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W1979375376","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W1976168335","https://openalex.org/W2109451123","https://openalex.org/W4378977321","https://openalex.org/W3211992815"],"abstract_inverted_index":{"High":[0],"energy":[1],"efficiency":[2],"and":[3,30,64,70,100,120,126],"high-capacity":[4],"embedded":[5],"SRAMs":[6],"are":[7,66],"essential":[8],"for":[9,51,68,123,134],"data-centric":[10,136],"applications.":[11,137],"CFET":[12,34,52,76,88,103],"technology":[13],"offers":[14],"a":[15,45,131],"scalable":[16],"solution":[17],"to":[18,36,75],"reduce":[19],"the":[20,25,97,102],"SRAM":[21,35,53,72,77,89,104],"cell":[22,58],"area.":[23],"However,":[24],"optimal":[26],"routing":[27,81],"of":[28],"signal":[29,80],"power":[31,84,122],"wires":[32],"in":[33],"achieve":[37],"better":[38],"performance":[39],"remains":[40],"unresolved.":[41],"This":[42,110],"study":[43],"proposes":[44],"Design":[46],"Technology":[47],"Co-Optimization":[48],"(DTCO)":[49],"framework":[50],"cells.":[54],"After":[55],"generating":[56],"3D":[57],"structures":[59],"through":[60],"layouts,":[61],"parasitic":[62,108],"resistance,":[63],"capacitance":[65],"analyzed":[67],"6T":[69,125],"8T":[71,127],"arrays.":[73],"Compared":[74],"using":[78],"single-sided":[79],"with":[82,90],"backside":[83],"delivery":[85],"network":[86],"(BS-PDN),":[87],"double-sided":[91],"signal/power":[92],"routing,":[93],"which":[94],"efficiently":[95],"leverages":[96],"space":[98],"above":[99],"below":[101],"cells,":[105],"exhibits":[106],"reduced":[107],"capacitance.":[109],"reduction":[111],"significantly":[112],"improves":[113],"read":[114,118],"delay,":[115,117],"write":[116,121],"power,":[119],"both":[124],"SRAMs,":[128],"making":[129],"it":[130],"promising":[132],"option":[133],"high-throughput":[135]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-11T08:14:18.477133","created_date":"2025-10-10T00:00:00"}