{"id":"https://openalex.org/W4411725233","doi":"https://doi.org/10.1109/iscas56072.2025.11043226","title":"REVBiT 2.0: REVerse Engineering of BiTstream for LUT Extraction, Boolean Logic, and Pin Combination Identification","display_name":"REVBiT 2.0: REVerse Engineering of BiTstream for LUT Extraction, Boolean Logic, and Pin Combination Identification","publication_year":2025,"publication_date":"2025-05-25","ids":{"openalex":"https://openalex.org/W4411725233","doi":"https://doi.org/10.1109/iscas56072.2025.11043226"},"language":"en","primary_location":{"id":"doi:10.1109/iscas56072.2025.11043226","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043226","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039018664","display_name":"Anmol Singh Narwariya","orcid":"https://orcid.org/0009-0003-9968-2151"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Anmol Singh Narwariya","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064074691","display_name":"Amit Paradkar","orcid":"https://orcid.org/0000-0003-3707-8939"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aniruddha Paradkar","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052017511","display_name":"Pabitra Das","orcid":"https://orcid.org/0000-0002-3511-5671"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pabitra Das","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044085104","display_name":"Amit Acharyya","orcid":"https://orcid.org/0000-0002-5636-0676"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Acharyya","raw_affiliation_strings":["Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,Department of Electrical Engineering,Hyderabad,India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5039018664"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16403614,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.699999988079071,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.699999988079071,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.718544602394104},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.7170476913452148},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7156827449798584},{"id":"https://openalex.org/keywords/identification","display_name":"Identification (biology)","score":0.5743066072463989},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.5577027201652527},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4846985340118408},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46805256605148315},{"id":"https://openalex.org/keywords/reverse-engineering","display_name":"Reverse engineering","score":0.4573255777359009},{"id":"https://openalex.org/keywords/extraction","display_name":"Extraction (chemistry)","score":0.43041643500328064},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.4258451461791992},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40742987394332886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39339935779571533},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3788515329360962},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3652556836605072},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18492701649665833},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17958605289459229},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.11537110805511475}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.718544602394104},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.7170476913452148},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7156827449798584},{"id":"https://openalex.org/C116834253","wikidata":"https://www.wikidata.org/wiki/Q2039217","display_name":"Identification (biology)","level":2,"score":0.5743066072463989},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.5577027201652527},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4846985340118408},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46805256605148315},{"id":"https://openalex.org/C207850805","wikidata":"https://www.wikidata.org/wiki/Q269608","display_name":"Reverse engineering","level":2,"score":0.4573255777359009},{"id":"https://openalex.org/C4725764","wikidata":"https://www.wikidata.org/wiki/Q844704","display_name":"Extraction (chemistry)","level":2,"score":0.43041643500328064},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.4258451461791992},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40742987394332886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39339935779571533},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3788515329360962},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3652556836605072},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18492701649665833},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17958605289459229},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.11537110805511475},{"id":"https://openalex.org/C59822182","wikidata":"https://www.wikidata.org/wiki/Q441","display_name":"Botany","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C43617362","wikidata":"https://www.wikidata.org/wiki/Q170050","display_name":"Chromatography","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas56072.2025.11043226","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas56072.2025.11043226","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1979603314","https://openalex.org/W2005006301","https://openalex.org/W2021705882","https://openalex.org/W2121029939","https://openalex.org/W2146369740","https://openalex.org/W2171549192","https://openalex.org/W2309268518","https://openalex.org/W2901623887","https://openalex.org/W2919561762","https://openalex.org/W3008388281","https://openalex.org/W4311839525","https://openalex.org/W4384009513","https://openalex.org/W4388505081","https://openalex.org/W4400233189","https://openalex.org/W6801074270"],"related_works":["https://openalex.org/W3040878082","https://openalex.org/W2802088203","https://openalex.org/W1497931871","https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2117956479","https://openalex.org/W2053477566","https://openalex.org/W4255564979","https://openalex.org/W2149339590"],"abstract_inverted_index":{"Field-Programmable":[0],"Gate":[1],"Arrays":[2],"(FPGAs)":[3],"are":[4],"extensively":[5],"utilized":[6,128],"in":[7,79,150,170],"various":[8],"fields":[9],"due":[10],"to":[11,17,50,120,145],"their":[12,190],"inherent":[13],"flexibility":[14],"and":[15,44,71,111,139,189,208,218,254,262,272,297],"ability":[16],"be":[18],"reconfigured.":[19],"The":[20,154,222],"functionality":[21],"of":[22,55,75,82,101,157,168,177,198,238],"digital":[23],"designs":[24],"within":[25,32],"FPGAs":[26],"is":[27,159,227],"stored":[28],"as":[29],"configuration":[30,167],"frames":[31],"the":[33,48,52,60,69,76,80,83,93,99,102,129,137,147,165,171,175,195,199,215,236,266,286,304],"bitstream.":[34,172,305],"Previous":[35],"studies":[36],"introduced":[37],"tools":[38],"like":[39],"BIL,":[40],"RapidSmith,":[41],"Debit,":[42],"DAT":[43],"BitFREE,":[45],"which":[46,135],"reverse-engineer":[47,121],"bitstream":[49,70,225,275],"reveal":[51],"Boolean":[53,141,191,219,300],"logic":[54,142,220,240,301],"Look-Up":[56],"Tables":[57],"(LUTs)":[58],"using":[59,265],"Xilinx":[61,84,104,131,251,268],"ISE":[62],"design":[63,78,106,270],"suite.":[64],"This":[65],"tool":[66],"produces":[67],"both":[68],"a":[72,184,231,239],"textual":[73],"representation":[74],"placed":[77],"form":[81],"Design":[85,133],"Language":[86],"(XDL)":[87],"file,":[88],"enabling":[89],"deeper":[90],"insights":[91],"into":[92],"FPGA\u2019s":[94],"internal":[95],"structure.":[96],"However,":[97],"with":[98,194,210,235],"introduction":[100],"AMD":[103,130,250,267],"Vivado":[105,132,269],"suite,":[107],"support":[108],"for":[109,163,186,214,224,259,285,294,299],"XDL":[110],"text-based":[112],"hardware":[113],"adjustments":[114],"discontinued,":[115],"making":[116],"it":[117],"more":[118,289],"challenging":[119],"modern":[122],"bitstreams.":[123],"Our":[124,201,242],"prior":[125],"study,":[126],"REVBiT,":[127],"Suite,":[134],"extracted":[136],"LUTs":[138,158,169,188,264],"identified":[140],"but":[143],"failed":[144],"identify":[146],"pin":[148,155,216,295],"combination":[149,156,217,296],"its":[151],"present":[152],"form.":[153],"also":[160],"essential":[161],"information":[162],"determining":[164],"correct":[166],"To":[173],"address":[174],"limitation":[176],"state-of-the-art":[178],"methods,":[179],"we":[180],"introduce":[181],"REVBiT":[182],"2.0,":[183],"methodology":[185,244],"extracting":[187],"logic,":[192],"along":[193],"pins":[196],"connection":[197],"LUT.":[200],"proposed":[202,243],"deep-learning":[203],"models":[204],"have":[205],"been":[206,246],"trained":[207],"tested":[209],"92,82,950":[211],"data":[212],"samples":[213],"identification.":[221],"experiment":[223],"extraction":[226],"carried":[228],"out":[229],"on":[230,249,274],"real":[232],"FPGA":[233,256],"board":[234],"help":[237],"analyzer.":[241],"has":[245],"experimentally":[247],"validated":[248],"7-Series,":[252],"Ultrascale,":[253],"Ultrascale+":[255],"device":[257],"families":[258],"2,":[260],"3,":[261],"4-input":[263],"suite":[271],"relying":[273],"without":[276],"any":[277],"additional":[278],"information.":[279],"We":[280],"achieved":[281],"\u2248":[282],"100%":[283],"accuracy":[284,293],"LUT":[287],"extraction,":[288],"than":[290],"87.50%":[291],"prediction":[292],"92.43%":[298],"identification":[302],"from":[303]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
