{"id":"https://openalex.org/W3158152144","doi":"https://doi.org/10.1109/iscas51556.2021.9401733","title":"A Novel Stochastic Polar Architecture for All-Digital Transmission","display_name":"A Novel Stochastic Polar Architecture for All-Digital Transmission","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3158152144","doi":"https://doi.org/10.1109/iscas51556.2021.9401733","mag":"3158152144"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029876453","display_name":"Chris Andriakopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Chris Andriakopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062509095","display_name":"Kleanthis Papachatzopoulos","orcid":"https://orcid.org/0000-0002-1193-7611"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Kleanthis Papachatzopoulos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021252086","display_name":"Vassilis Paliouras","orcid":"https://orcid.org/0000-0002-1414-7500"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Vassilis Paliouras","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5029876453"],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.1671,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.43077998,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"58","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.7498777508735657},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7269786596298218},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5731738209724426},{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.5590100288391113},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4645269811153412},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4511132538318634},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.4459567070007324},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.409170538187027},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39249804615974426},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3672953248023987},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36487966775894165},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3422917127609253},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20432066917419434},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1980816125869751},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17936694622039795},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12897717952728271},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11974036693572998},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.09906506538391113}],"concepts":[{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.7498777508735657},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7269786596298218},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5731738209724426},{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.5590100288391113},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4645269811153412},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4511132538318634},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.4459567070007324},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.409170538187027},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39249804615974426},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3672953248023987},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36487966775894165},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3422917127609253},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20432066917419434},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1980816125869751},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17936694622039795},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12897717952728271},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11974036693572998},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.09906506538391113},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1558145334","https://openalex.org/W1949681705","https://openalex.org/W1982781260","https://openalex.org/W1983424048","https://openalex.org/W2044829853","https://openalex.org/W2047942249","https://openalex.org/W2049931245","https://openalex.org/W2084424389","https://openalex.org/W2118240018","https://openalex.org/W2120901787","https://openalex.org/W2125270192","https://openalex.org/W2129380712","https://openalex.org/W2157348988","https://openalex.org/W2337655349","https://openalex.org/W2539422612","https://openalex.org/W2782989621","https://openalex.org/W2800111511","https://openalex.org/W2808351619","https://openalex.org/W2993245516","https://openalex.org/W3049743334","https://openalex.org/W3089680622","https://openalex.org/W6677308760"],"related_works":["https://openalex.org/W2375598816","https://openalex.org/W2163289731","https://openalex.org/W2373124540","https://openalex.org/W2391017997","https://openalex.org/W1598263934","https://openalex.org/W2375622460","https://openalex.org/W2545292255","https://openalex.org/W189219268","https://openalex.org/W2973137837","https://openalex.org/W2159352256"],"abstract_inverted_index":{"A":[0],"novel":[1],"architecture":[2,22,73],"of":[3,26,33,59,68,80,89,94],"an":[4,34],"all-digital":[5,35,71],"transmitter":[6,36,98],"is":[7,43,85],"proposed":[8,21,96],"in":[9,54],"this":[10],"paper,":[11],"introducing":[12],"stochastic":[13,27,56],"computation":[14],"to":[15,29,61,87,115],"a":[16,47,51,90,100],"single-bit":[17],"polar":[18,72],"topology.":[19],"The":[20],"exploits":[23],"the":[24,31,55,69,76,81,95],"benefits":[25],"computing":[28],"simplify":[30],"design":[32],"and":[37,110],"minimize":[38],"hardware":[39],"complexity.":[40],"Complexity":[41],"reduction":[42,113],"achieved":[44],"by":[45],"implementing":[46],"digital":[48],"oscillator":[49],"as":[50],"cosine":[52],"function":[53],"domain":[57],"instead":[58],"resorting":[60],"LUT-based":[62],"or":[63],"CORDIC-based":[64],"implementations.":[65,117],"An":[66],"evaluation":[67],"introduced":[70],"shows":[74],"that":[75,88],"power":[77],"spectral":[78],"density":[79],"transmitted":[82],"passband":[83],"signal":[84],"similar":[86],"conventional":[91,116],"transmitter.":[92],"Synthesis":[93],"stochastic-enabled":[97],"at":[99],"28-nm":[101],"FDSOI":[102],"technology":[103],"node":[104],"reveals":[105],"its":[106],"minimal":[107],"complexity":[108],"requirements":[109],"87.13%":[111],"area":[112],"compared":[114]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}