{"id":"https://openalex.org/W3157387931","doi":"https://doi.org/10.1109/iscas51556.2021.9401425","title":"Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths","display_name":"Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3157387931","doi":"https://doi.org/10.1109/iscas51556.2021.9401425","mag":"3157387931"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401425","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401425","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088097531","display_name":"Inbal Stanger","orcid":"https://orcid.org/0000-0002-9038-1278"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Inbal Stanger","raw_affiliation_strings":["Bar-Ilan University, Ramat-Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043898382","display_name":"Netanel Shavit","orcid":"https://orcid.org/0000-0003-2011-6329"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Netanel Shavit","raw_affiliation_strings":["Bar-Ilan University, Ramat-Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004107991","display_name":"Ramiro Taco","orcid":"https://orcid.org/0000-0003-3046-2364"},"institutions":[{"id":"https://openalex.org/I69094615","display_name":"Universidad San Francisco de Quito","ror":"https://ror.org/01r2c3v86","country_code":"EC","type":"education","lineage":["https://openalex.org/I69094615"]}],"countries":["EC"],"is_corresponding":false,"raw_author_name":"Ramiro Taco","raw_affiliation_strings":["Universidad San Francisco de Quito, Quito, Ecuador"],"affiliations":[{"raw_affiliation_string":"Universidad San Francisco de Quito, Quito, Ecuador","institution_ids":["https://openalex.org/I69094615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016654766","display_name":"Marco Lanuzza","orcid":"https://orcid.org/0000-0002-6480-9218"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Lanuzza","raw_affiliation_strings":["University of Calabria, Cosenza, Italy"],"affiliations":[{"raw_affiliation_string":"University of Calabria, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065902823","display_name":"Alexander Fish","orcid":"https://orcid.org/0000-0002-4994-1536"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Alexander Fish","raw_affiliation_strings":["Bar-Ilan University, Ramat-Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5088097531"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0345916,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-mode-optical-fiber","display_name":"Multi-mode optical fiber","score":0.767189085483551},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6234055161476135},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5792307257652283},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5270852446556091},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5216348767280579},{"id":"https://openalex.org/keywords/ranging","display_name":"Ranging","score":0.4617031216621399},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4496595561504364},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4458867311477661},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.42357516288757324},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.378390908241272},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25815320014953613},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21883660554885864},{"id":"https://openalex.org/keywords/optical-fiber","display_name":"Optical fiber","score":0.07986623048782349},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07492789626121521}],"concepts":[{"id":"https://openalex.org/C101645829","wikidata":"https://www.wikidata.org/wiki/Q1781857","display_name":"Multi-mode optical fiber","level":3,"score":0.767189085483551},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6234055161476135},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5792307257652283},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5270852446556091},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5216348767280579},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.4617031216621399},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4496595561504364},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4458867311477661},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.42357516288757324},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.378390908241272},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25815320014953613},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21883660554885864},{"id":"https://openalex.org/C194232370","wikidata":"https://www.wikidata.org/wiki/Q162","display_name":"Optical fiber","level":2,"score":0.07986623048782349},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07492789626121521},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401425","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401425","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2913907525","https://openalex.org/W3046363520"],"related_works":["https://openalex.org/W2783354812","https://openalex.org/W4384112194","https://openalex.org/W2103009189","https://openalex.org/W4312958259","https://openalex.org/W2349383066","https://openalex.org/W1969901537","https://openalex.org/W4328132048","https://openalex.org/W4308259661","https://openalex.org/W1639545646","https://openalex.org/W2376202349"],"abstract_inverted_index":{"This":[0],"demo":[1],"demonstrates":[2],"the":[3,7,70,73],"unique":[4],"capabilities":[5],"of":[6,72],"multimode":[8],"Dual":[9],"Mode":[10],"Logic":[11],"(DML)":[12],"design":[13],"technique":[14],"to":[15,20,54,65,76],"define":[16],"run-time":[17],"adaptive":[18],"datapaths":[19],"overcome":[21],"process":[22],"and":[23,27,37,56,83],"environmental":[24],"(i.e.,":[25],"temperature":[26,57,84],"voltage)":[28],"variations.":[29,86],"A":[30],"proof-of":[31],"concept":[32],"benchmark":[33],"circuit":[34],"is":[35],"designed":[36],"fabricated":[38],"in":[39],"65":[40],"nm":[41],"technology.":[42],"Measurements":[43],"on":[44],"10":[45],"test":[46],"chips,":[47],"while":[48],"considering":[49],"supply":[50],"voltages":[51],"spanning":[52],"0.6V":[53],"1.2V":[55],"variations":[58],"ranging":[59],"from":[60],"-":[61],"40":[62],"\u00b0":[63,67],"C":[64,68],"125":[66],"confirmed":[69],"effectiveness":[71],"proposed":[74],"approach":[75],"compensate":[77],"even":[78],"for":[79],"severe":[80],"process,":[81],"voltage":[82],"(PVT)":[85]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}