{"id":"https://openalex.org/W3157465175","doi":"https://doi.org/10.1109/iscas51556.2021.9401308","title":"Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars","display_name":"Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3157465175","doi":"https://doi.org/10.1109/iscas51556.2021.9401308","mag":"3157465175"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100768143","display_name":"Weiyi Liu","orcid":"https://orcid.org/0000-0003-4835-7861"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weiyi Liu","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102022581","display_name":"Yanan Sun","orcid":"https://orcid.org/0000-0001-8281-9121"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanan Sun","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101583945","display_name":"Weifeng He","orcid":"https://orcid.org/0000-0002-7753-644X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weifeng He","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100422764","display_name":"Qin Wang","orcid":"https://orcid.org/0000-0001-6824-1351"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qin Wang","raw_affiliation_strings":["Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100768143"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.5014,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.62929749,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12236","display_name":"Photoreceptor and optogenetics research","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6875725984573364},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.667748212814331},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6362727880477905},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.621161699295044},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5806925296783447},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5765135288238525},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5496575832366943},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5269713401794434},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5134426355361938},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4863877594470978},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.42323172092437744},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.4149585962295532},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3912692070007324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3716046214103699},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.29669326543807983},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24378925561904907},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.1569732129573822},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1496715247631073},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14114701747894287},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.12055715918540955},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10988268256187439},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07473048567771912}],"concepts":[{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6875725984573364},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.667748212814331},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6362727880477905},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.621161699295044},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5806925296783447},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5765135288238525},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5496575832366943},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5269713401794434},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5134426355361938},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4863877594470978},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.42323172092437744},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.4149585962295532},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3912692070007324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3716046214103699},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29669326543807983},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24378925561904907},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.1569732129573822},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1496715247631073},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14114701747894287},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.12055715918540955},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10988268256187439},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07473048567771912},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401308","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W189008600","https://openalex.org/W1526219215","https://openalex.org/W2025674646","https://openalex.org/W2066280488","https://openalex.org/W2069313594","https://openalex.org/W2081729575","https://openalex.org/W2162279286","https://openalex.org/W2169245181","https://openalex.org/W2407339173","https://openalex.org/W2419663043","https://openalex.org/W2765894485","https://openalex.org/W2895774650","https://openalex.org/W2934968350","https://openalex.org/W2972614379","https://openalex.org/W3013318343","https://openalex.org/W3101159937","https://openalex.org/W3216272643"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2017528947","https://openalex.org/W1553855433","https://openalex.org/W1593362825","https://openalex.org/W1529529399","https://openalex.org/W2082591327","https://openalex.org/W2155174752","https://openalex.org/W2102499515","https://openalex.org/W2171918386","https://openalex.org/W2021357106"],"abstract_inverted_index":{"Implementing":[0],"logic":[1,20,23,30,73,79,125,150],"within":[2],"memristive":[3,54,124],"crossbar":[4],"is":[5,49,136],"an":[6],"attractive":[7],"approach":[8],"to":[9,38,93,116,141,145],"overcome":[10],"the":[11,27,34,39,53,58,65,90,96,103,107,132],"memory":[12],"wall":[13],"in":[14,89],"conventional":[15],"von":[16],"Neumann":[17],"architectures.":[18],"Ternary":[19],"with":[21,120],"three":[22],"levels":[24],"can":[25],"reduce":[26,95],"number":[28],"of":[29,68,106],"operations":[31,86],"and":[32,60,75,84],"enhance":[33],"computing":[35],"speed":[36],"compared":[37,119,144],"binary":[40,78,123,148],"logic.":[41],"In":[42],"this":[43],"paper,":[44],"a":[45],"ternary":[46,72,110,134],"logic-in-memory":[47],"scheme":[48,92],"proposed":[50,91,108,133],"based":[51],"on":[52],"dual-crossbar":[55],"structure":[56],"where":[57],"inputs":[59],"outputs":[61],"are":[62,87,112],"represented":[63],"by":[64,114,131,139],"multi-level":[66],"cells":[67],"memristors.":[69],"Two":[70],"inter-crossbar":[71],"gates":[74],"one":[76],"intra-crossbar":[77],"gate":[80],"for":[81],"both":[82],"row":[83],"column-wise":[85],"supported":[88],"effectively":[94],"operation":[97,104],"latency.":[98],"Experimental":[99],"results":[100],"show":[101],"that":[102],"steps":[105],"multi-trit":[109],"adder":[111,135],"reduced":[113,138],"up":[115,140],"83.82%,":[117],"as":[118,143],"previously":[121,146],"published":[122,147],"designs.":[126],"The":[127],"computation":[128],"energy":[129],"consumed":[130],"also":[137],"35.87%":[142],"IMPLY":[149],"design.":[151]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
