{"id":"https://openalex.org/W3157056359","doi":"https://doi.org/10.1109/iscas51556.2021.9401291","title":"Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs","display_name":"Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3157056359","doi":"https://doi.org/10.1109/iscas51556.2021.9401291","mag":"3157056359"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023111714","display_name":"Kurea Murakami","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Kurea Murakami","raw_affiliation_strings":["Electrical and Electronic Engineering Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101887712","display_name":"Minoru Watanabe","orcid":"https://orcid.org/0000-0002-7452-3555"},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Minoru Watanabe","raw_affiliation_strings":["Electrical and Electronic Engineering Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5023111714"],"corresponding_institution_ids":["https://openalex.org/I1298590031"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.40315916,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/data-scrubbing","display_name":"Data scrubbing","score":0.9246510863304138},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8554602861404419},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.7271838188171387},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7216359376907349},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4940533936023712},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4906376898288727},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4455919861793518},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4141845703125},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15931913256645203},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14837661385536194},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07604935765266418}],"concepts":[{"id":"https://openalex.org/C89529581","wikidata":"https://www.wikidata.org/wiki/Q5227348","display_name":"Data scrubbing","level":2,"score":0.9246510863304138},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8554602861404419},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.7271838188171387},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7216359376907349},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4940533936023712},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4906376898288727},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4455919861793518},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4141845703125},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15931913256645203},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14837661385536194},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07604935765266418},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W2021798215","https://openalex.org/W2023390220","https://openalex.org/W2041252144","https://openalex.org/W2055871370","https://openalex.org/W2065342367","https://openalex.org/W2084982468","https://openalex.org/W2085955608","https://openalex.org/W2121336511","https://openalex.org/W2138015649","https://openalex.org/W2176722529","https://openalex.org/W2291356006","https://openalex.org/W2559957313","https://openalex.org/W2601634806","https://openalex.org/W2735185372","https://openalex.org/W2756939253","https://openalex.org/W2758452756","https://openalex.org/W2760502342","https://openalex.org/W2767108248","https://openalex.org/W2895588716","https://openalex.org/W2951677078","https://openalex.org/W2964316497","https://openalex.org/W2966099395","https://openalex.org/W2981551676","https://openalex.org/W3003481615","https://openalex.org/W3016079222","https://openalex.org/W3028989297","https://openalex.org/W3108130890","https://openalex.org/W4253075282"],"related_works":["https://openalex.org/W3144951481","https://openalex.org/W4399458808","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2072850836","https://openalex.org/W1968650434","https://openalex.org/W2105610663","https://openalex.org/W1996607072"],"abstract_inverted_index":{"This":[0,91],"paper":[1,92],"presents":[2,93],"a":[3,6,61,72,77],"proposal":[4],"for":[5,11],"sequential":[7,40,53,62],"circuit":[8,63,81],"implementation":[9],"method":[10],"multi-context":[12,25,57,73],"scrubbing":[13,26,58,74],"operations":[14,27],"that":[15,98],"can":[16,28],"treat":[17,29],"soft-error":[18],"and":[19],"permanent":[20,30],"failure":[21,31],"issues":[22,32],"simultaneously.":[23],"Although":[24],"on":[33,86],"field":[34],"programmable":[35],"gate":[36],"arrays":[37],"(FPGAs),":[38],"implementing":[39],"circuits":[41],"is":[42],"difficult":[43],"because":[44],"the":[45],"flip-flop":[46],"location":[47],"must":[48],"be":[49],"changed":[50],"while":[51],"maintaining":[52],"operations.":[54],"Therefore,":[55],"no":[56],"operation":[59,75],"including":[60],"has":[64,82],"been":[65,83],"demonstrated":[66,84],"to":[67],"date.":[68],"As":[69],"described":[70],"herein,":[71],"using":[76],"simple":[78],"8-bit":[79],"counter":[80],"perfectly":[85],"an":[87],"Artix-7":[88],"FPGA":[89],"(XC7A35TICSG324-1L).":[90],"experimentally":[94],"obtained":[95],"results":[96],"of":[97],"demonstration.":[99]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
