{"id":"https://openalex.org/W3159889753","doi":"https://doi.org/10.1109/iscas51556.2021.9401273","title":"A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS","display_name":"A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3159889753","doi":"https://doi.org/10.1109/iscas51556.2021.9401273","mag":"3159889753"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401273","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401273","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037582044","display_name":"Frowin Buballa","orcid":"https://orcid.org/0000-0003-2659-0152"},"institutions":[{"id":"https://openalex.org/I4577782","display_name":"Technische Universit\u00e4t Berlin","ror":"https://ror.org/03v4gjf40","country_code":"DE","type":"education","lineage":["https://openalex.org/I4577782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Frowin Buballa","raw_affiliation_strings":["Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany","institution_ids":["https://openalex.org/I4577782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005078790","display_name":"Sebastian Linnhoff","orcid":"https://orcid.org/0000-0002-9598-2291"},"institutions":[{"id":"https://openalex.org/I4577782","display_name":"Technische Universit\u00e4t Berlin","ror":"https://ror.org/03v4gjf40","country_code":"DE","type":"education","lineage":["https://openalex.org/I4577782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Linnhoff","raw_affiliation_strings":["Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany","institution_ids":["https://openalex.org/I4577782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033425038","display_name":"Michael Reinhold","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michael Reinhold","raw_affiliation_strings":["eesy-ic GmbH, Erlangen, Germany"],"affiliations":[{"raw_affiliation_string":"eesy-ic GmbH, Erlangen, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032302022","display_name":"Friedel Gerfers","orcid":"https://orcid.org/0000-0002-0520-1923"},"institutions":[{"id":"https://openalex.org/I4577782","display_name":"Technische Universit\u00e4t Berlin","ror":"https://ror.org/03v4gjf40","country_code":"DE","type":"education","lineage":["https://openalex.org/I4577782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Friedel Gerfers","raw_affiliation_strings":["Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Chair Mixed Signal Circuit Design, Technische Universit\u00e4t, Berlin, Germany","institution_ids":["https://openalex.org/I4577782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5037582044"],"corresponding_institution_ids":["https://openalex.org/I4577782"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.04363385,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.8418241739273071},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.7961834073066711},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.7294777631759644},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6021353602409363},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5801483392715454},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5543721914291382},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5061764121055603},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.4868185222148895},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.4216095209121704},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.36694103479385376},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3433595895767212},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3200622797012329},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.242327481508255}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.8418241739273071},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.7961834073066711},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.7294777631759644},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6021353602409363},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5801483392715454},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5543721914291382},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5061764121055603},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.4868185222148895},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.4216095209121704},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.36694103479385376},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3433595895767212},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3200622797012329},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.242327481508255},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401273","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401273","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1806144281","https://openalex.org/W1977624377","https://openalex.org/W2107169806","https://openalex.org/W2592547566","https://openalex.org/W2592879599","https://openalex.org/W2898702326","https://openalex.org/W3015454294","https://openalex.org/W3024999395","https://openalex.org/W3114738544","https://openalex.org/W6777977541","https://openalex.org/W6787990305"],"related_works":["https://openalex.org/W2783221760","https://openalex.org/W2759515872","https://openalex.org/W4206356469","https://openalex.org/W2904640696","https://openalex.org/W2341231357","https://openalex.org/W2942561789","https://openalex.org/W2511822798","https://openalex.org/W4390693196","https://openalex.org/W2054018984","https://openalex.org/W2082979872"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,45,79,87,92,107,115,122,130,150,154,204,245],"design":[4],"of":[5,98,109,117,156,189,200,234,244],"a":[6,31,34,99,118,133,157,183,212],"subsampling":[7],"wideband":[8],"500":[9],"MS/s":[10],"12":[11,68],"Bit":[12,69],"successive-approximation-register":[13],"(SAR)":[14],"analog-to-digital":[15],"converter":[16],"(ADC)":[17],"with":[18],"sub-2":[19],"radix":[20,63],"split-":[21],"capacitor":[22],"array":[23],"(SCA).":[24],"The":[25,96,177,227,240],"presented":[26],"ADC":[27,48,180,248],"is":[28,64,104,140,249],"designed":[29],"as":[30],"sub-ADC":[32,172,218],"for":[33],"sample-and-hold-less":[35],"(SAH-less)":[36],"8":[37],"GS/s":[38],"time-interleaved":[39,163],"(TI)":[40],"ADC.":[41],"In":[42],"addition":[43],"to":[44,66,173,194],"required":[46],"16":[47],"channels,":[49],"two":[50],"additional":[51,146],"SAR":[52,82,123,151],"lanes":[53],"enable":[54,81],"pseudorandom":[55],"binary":[56],"sequence":[57],"(PRBS)-driven":[58],"channel":[59,164],"scrambling.":[60],"A":[61],"1.81":[62],"used":[65],"achieve":[67],"settling":[70],"accuracy":[71],"withing":[72],"70":[73],"ps.":[74],"Extra":[75],"scaling":[76],"capacitors":[77],"in":[78,211],"SCA":[80,93,161],"reference":[83],"voltage":[84],"levels":[85],"near":[86],"supply":[88,232],"rails,":[89],"significantly":[90],"reducing":[91],"switch":[94],"sizes.":[95],"necessity":[97],"comparator":[100,111,120],"latch":[101],"reset":[102,147],"phase":[103,148],"eliminated":[105,142],"at":[106],"cost":[108],"higher":[110],"power":[112,242],"consumption":[113,243],"by":[114,143,169],"adoption":[116],"loop-unrolled":[119],"improving":[121],"loop":[124],"timing.":[125],"Top-plate":[126],"charge":[127],"kickback":[128],"into":[129],"input":[131,159,228],"buffer,":[132],"challenge":[134],"that":[135],"occurs":[136],"within":[137,149],"TI":[138,247],"ADCs,":[139],"largely":[141],"implementing":[144],"an":[145,174],"algorithm":[152],"and":[153,162,192,196,225,237],"use":[155],"boosted":[158],"T-switch.":[160],"mismatch":[165],"effects":[166],"are":[167],"addressed":[168],"calibrating":[170],"each":[171,217],"extra":[175],"reference-ADC.":[176],"industry":[178],"grade":[179],"design,":[181],"achieves":[182],"spurious":[184],"free":[185],"dynamic":[186],"range":[187],"(SFDR)":[188],"72":[190],"dB":[191,202],"signal":[193],"noise":[195],"distortion":[197],"ratio":[198],"(SNDR)":[199],"54":[201],"across":[203],"entire":[205],"4":[206],"GHz":[207],"frequency":[208],"range.":[209],"Designed":[210],"28":[213],"nm":[214],"CMOS":[215],"process,":[216],"consumes":[219],"33":[220],"mW":[221],"from":[222],"1.8":[223],"V":[224,236],"1V.":[226],"buffer":[229],"frontend":[230],"uses":[231],"voltages":[233],"2.5":[235],"-1.3":[238],"V.":[239],"overall":[241,246],"3":[250],"W.":[251]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}