{"id":"https://openalex.org/W3158521913","doi":"https://doi.org/10.1109/iscas51556.2021.9401210","title":"An RS (255,239) Decoder with e-PIBM Algorithm, 25.6Gb/s Throughput and 623 TSNT FoM Value Using Fractional Folding Technique in 40nm Technology","display_name":"An RS (255,239) Decoder with e-PIBM Algorithm, 25.6Gb/s Throughput and 623 TSNT FoM Value Using Fractional Folding Technique in 40nm Technology","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3158521913","doi":"https://doi.org/10.1109/iscas51556.2021.9401210","mag":"3158521913"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401210","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401210","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100343176","display_name":"Wenwen Liu","orcid":"https://orcid.org/0000-0003-1082-4401"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wenwen Liu","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115593820","display_name":"Gang Wang","orcid":"https://orcid.org/0000-0003-0252-488X"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gang Wang","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087674100","display_name":"Qinghao Lin","orcid":"https://orcid.org/0000-0002-4405-0830"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qinghao Lin","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115602439","display_name":"Haibo Liu","orcid":"https://orcid.org/0000-0002-4213-2883"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haibo Liu","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037758320","display_name":"Jing-Wei Shi","orcid":null},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jingwei Shi","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100616299","display_name":"Min Lin","orcid":"https://orcid.org/0000-0001-7042-9601"},"institutions":[{"id":"https://openalex.org/I113940042","display_name":"Shanghai University","ror":"https://ror.org/006teas31","country_code":"CN","type":"education","lineage":["https://openalex.org/I113940042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Min Lin","raw_affiliation_strings":["Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Advanced SoC and IoT Technology Lab Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China","institution_ids":["https://openalex.org/I113940042"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100343176"],"corresponding_institution_ids":["https://openalex.org/I113940042"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05217202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"138","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11797","display_name":"graph theory and CDMA systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7359573841094971},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7122102975845337},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.6858411431312561},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6345833539962769},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6267423629760742},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6041065454483032},{"id":"https://openalex.org/keywords/gate-count","display_name":"Gate count","score":0.5862892270088196},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5166540741920471},{"id":"https://openalex.org/keywords/polyphase-system","display_name":"Polyphase system","score":0.4680008292198181},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.44150251150131226},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4100533723831177},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4032030701637268},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40085268020629883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2876124680042267},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2361733615398407},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11410164833068848},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10447099804878235},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09562990069389343}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7359573841094971},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7122102975845337},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.6858411431312561},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6345833539962769},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6267423629760742},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6041065454483032},{"id":"https://openalex.org/C2777892113","wikidata":"https://www.wikidata.org/wiki/Q5527005","display_name":"Gate count","level":2,"score":0.5862892270088196},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5166540741920471},{"id":"https://openalex.org/C96157337","wikidata":"https://www.wikidata.org/wiki/Q391639","display_name":"Polyphase system","level":2,"score":0.4680008292198181},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.44150251150131226},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4100533723831177},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4032030701637268},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40085268020629883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2876124680042267},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2361733615398407},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11410164833068848},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10447099804878235},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09562990069389343},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401210","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401210","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1514022891","https://openalex.org/W1970132958","https://openalex.org/W2042117344","https://openalex.org/W2075850503","https://openalex.org/W2101402725","https://openalex.org/W2118501221","https://openalex.org/W2122075089","https://openalex.org/W2162442687","https://openalex.org/W2169940852","https://openalex.org/W2171876558","https://openalex.org/W2226663035","https://openalex.org/W2276650142","https://openalex.org/W2551395885","https://openalex.org/W2742306459","https://openalex.org/W2803008395"],"related_works":["https://openalex.org/W2062123576","https://openalex.org/W2601586183","https://openalex.org/W2106127105","https://openalex.org/W3123703559","https://openalex.org/W2402147443","https://openalex.org/W3118502605","https://openalex.org/W2808532520","https://openalex.org/W4301955845","https://openalex.org/W803071933","https://openalex.org/W3123827098"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,19,144,156,162],"novel":[4],"Fractional":[5,20],"Folding":[6,21],"(FF)":[7],"architecture":[8,54,113,128],"for":[9],"digital":[10],"signal":[11,75],"processing":[12,37],"integrated":[13],"circuits.":[14],"With":[15],"this":[16,170],"new":[17],"structure,":[18],"based":[22],"enhanced":[23],"Parallel":[24],"Inversionless":[25],"Berlekamp-Massey":[26],"(FF-ePIBM)":[27],"Reed-Solomon":[28],"Decoder":[29],"is":[30,76,90,114,129],"presented":[31],"of":[32,36,110,147,159,167],"which":[33],"the":[34,58,66,108,141],"number":[35],"element":[38],"(PE)":[39],"can":[40,55,150],"be":[41],"reduced":[42],"to":[43,65,80,86,116,154,169],"only":[44],"one,":[45],"resulting":[46],"in":[47,78,99],"ultra-low":[48],"hardware":[49,59],"complexity.":[50],"The":[51,121,136],"FF-ePIBM":[52,127],"VLSI":[53,102],"greatly":[56],"reduce":[57],"cost":[60],"by":[61],"about":[62],"60%":[63],"compare":[64],"fully":[67],"expanded":[68],"parallel":[69],"ePIBM":[70],"architecture.":[71],"A":[72],"polyphase":[73],"clock":[74],"needed":[77],"order":[79],"achieve":[81,155],"fractional":[82],"folding":[83],"function":[84],"according":[85],"specific":[87],"fractional-factor.":[88],"It":[89],"generated":[91],"from":[92],"Delay":[93],"Locked":[94],"Loop":[95],"(DLL)":[96],"commonly":[97],"embedded":[98],"almost":[100],"all":[101],"circuit":[103],"and":[104,149,161],"system.":[105],"To":[106],"maximize":[107],"throughput":[109,158],"decoder,":[111],"pipelined":[112],"adopted":[115],"optimize":[117],"critical":[118],"path":[119],"delay.":[120],"RS":[122],"(255,":[123],"239)":[124],"decoder":[125,142],"with":[126,132],"finally":[130],"implemented":[131],"40nm":[133],"CMOS":[134],"technology.":[135],"synthesized":[137],"results":[138],"demonstrate":[139],"that":[140],"has":[143],"gate":[145],"count":[146],"12.6k":[148],"operate":[151],"at":[152],"3.2GHz":[153],"highest":[157],"25.6Gb/s":[160],"best":[163],"TSNT":[164],"FoM":[165],"value":[166],"623":[168],"date.":[171]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}