{"id":"https://openalex.org/W3158227880","doi":"https://doi.org/10.1109/iscas51556.2021.9401150","title":"Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes","display_name":"Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3158227880","doi":"https://doi.org/10.1109/iscas51556.2021.9401150","mag":"3158227880"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100407149","display_name":"Chao Wang","orcid":"https://orcid.org/0000-0003-4836-7648"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chao Wang","raw_affiliation_strings":["Fert Beijing Research Institute, Beihang University, Beijing, China","School of Electronics and Information Engineering, Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Fert Beijing Research Institute, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"School of Electronics and Information Engineering, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056897117","display_name":"Zhaohao Wang","orcid":"https://orcid.org/0000-0002-2999-7903"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhaohao Wang","raw_affiliation_strings":["Fert Beijing Research Institute, Beihang University, Beijing, China","MIIT Key Laboratory of Spintronics, Beihang University, Beijing, China","School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Fert Beijing Research Institute, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"MIIT Key Laboratory of Spintronics, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018693228","display_name":"Youguang Zhang","orcid":"https://orcid.org/0009-0008-0928-4210"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Youguang Zhang","raw_affiliation_strings":["Fert Beijing Research Institute, Beihang University, Beijing, China","School of Electronics and Information Engineering, Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Fert Beijing Research Institute, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"School of Electronics and Information Engineering, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109540745","display_name":"Weisheng Zhao","orcid":"https://orcid.org/0009-0003-1386-4887"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weisheng Zhao","raw_affiliation_strings":["Fert Beijing Research Institute, Beihang University, Beijing, China","MIIT Key Laboratory of Spintronics, Beihang University, Beijing, China","School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Fert Beijing Research Institute, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"MIIT Key Laboratory of Spintronics, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100407149"],"corresponding_institution_ids":["https://openalex.org/I82880672"],"apc_list":null,"apc_paid":null,"fwci":0.601,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.66728701,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"53","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7828608155250549},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.7632615566253662},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5972074270248413},{"id":"https://openalex.org/keywords/spin-transfer-torque","display_name":"Spin-transfer torque","score":0.5228786468505859},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5189668536186218},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.49424436688423157},{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.4843824803829193},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.46559035778045654},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46306246519088745},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4463747441768646},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4422135055065155},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.43654322624206543},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4328697621822357},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4324910044670105},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.32394129037857056},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2876540720462799},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.26657652854919434},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1243884265422821}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7828608155250549},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.7632615566253662},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5972074270248413},{"id":"https://openalex.org/C609986","wikidata":"https://www.wikidata.org/wiki/Q844840","display_name":"Spin-transfer torque","level":4,"score":0.5228786468505859},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5189668536186218},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.49424436688423157},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.4843824803829193},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.46559035778045654},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46306246519088745},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4463747441768646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4422135055065155},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.43654322624206543},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4328697621822357},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4324910044670105},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.32394129037857056},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2876540720462799},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.26657652854919434},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1243884265422821},{"id":"https://openalex.org/C32546565","wikidata":"https://www.wikidata.org/wiki/Q856711","display_name":"Magnetization","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115260700","wikidata":"https://www.wikidata.org/wiki/Q11408","display_name":"Magnetic field","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2024122052","https://openalex.org/W2081729575","https://openalex.org/W2103954785","https://openalex.org/W2110276925","https://openalex.org/W2118531588","https://openalex.org/W2396622873","https://openalex.org/W2593172471","https://openalex.org/W2615320339","https://openalex.org/W2747816535","https://openalex.org/W2920042105","https://openalex.org/W2941172511","https://openalex.org/W2942415134","https://openalex.org/W3002919214","https://openalex.org/W3046225739","https://openalex.org/W3049464145","https://openalex.org/W3105500088","https://openalex.org/W4240306535","https://openalex.org/W4243585432","https://openalex.org/W6738375554"],"related_works":["https://openalex.org/W2809950606","https://openalex.org/W2913283152","https://openalex.org/W4382698721","https://openalex.org/W4206064298","https://openalex.org/W4205450031","https://openalex.org/W2951266691","https://openalex.org/W2792072658","https://openalex.org/W4388285079","https://openalex.org/W3046969929","https://openalex.org/W2737211761"],"abstract_inverted_index":{"With":[0],"the":[1,13,33,80,84,91,97,112,120],"surge":[2],"in":[3,10,36],"demand":[4],"for":[5],"data":[6],"storage":[7],"and":[8,25,75,96,108,115],"processing":[9],"emerging":[11],"applications,":[12],"traditional":[14],"CMOS-based":[15],"Von-Neumann":[16],"architecture":[17],"is":[18],"facing":[19],"challenges":[20],"such":[21],"as":[22],"memory":[23,46,67],"wall":[24],"static":[26],"power":[27,117],"consumption.":[28],"In":[29,52,110],"order":[30],"to":[31,101],"conquer":[32],"above-mentioned":[34],"bottlenecks":[35],"computing":[37,39],"systems,":[38],"in-memory":[40],"(CiM)":[41],"architectures":[42],"based":[43,60],"on":[44,61],"non-volatile":[45],"(NVM)":[47],"have":[48],"been":[49],"widely":[50],"researched.":[51],"this":[53],"paper,":[54],"we":[55],"propose":[56],"a":[57,130],"CiM":[58,122],"paradigm":[59,123],"spin-transfer":[62],"torque":[63],"magnetic":[64],"random":[65],"access":[66],"(STT-MRAM),":[68],"which":[69],"combines":[70],"common":[71],"read-like":[72],"mode":[73,77],"(RLM)":[74],"write-like":[76],"(WLM).":[78],"On":[79],"basis":[81],"of":[82,94,99,119],"realizing":[83],"basic":[85],"functions":[86],"AND/OR/NAND/NOR,":[87],"our":[88],"design":[89,133],"coordinates":[90],"high":[92,113],"speed":[93,114],"RLM":[95],"integrity":[98],"WLM":[100],"perform":[102],"complex":[103],"operations":[104],"like":[105],"full-adder":[106],"(FA)":[107],"XOR/XNOR.":[109],"addition,":[111],"low":[116],"consumption":[118],"proposed":[121],"are":[124],"established":[125],"by":[126],"circuit-level":[127],"simulation":[128],"with":[129],"40":[131],"nm":[132],"kit.":[134]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}