{"id":"https://openalex.org/W3158939455","doi":"https://doi.org/10.1109/iscas51556.2021.9401058","title":"PlasticNet+: Extending Multi-FPGA Interconnect Architecture via Gigabit Transceivers","display_name":"PlasticNet+: Extending Multi-FPGA Interconnect Architecture via Gigabit Transceivers","publication_year":2021,"publication_date":"2021-04-27","ids":{"openalex":"https://openalex.org/W3158939455","doi":"https://doi.org/10.1109/iscas51556.2021.9401058","mag":"3158939455"},"language":"en","primary_location":{"id":"doi:10.1109/iscas51556.2021.9401058","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401058","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061035642","display_name":"Carlos Salazar-Garc\u00eda","orcid":"https://orcid.org/0000-0002-9453-8228"},"institutions":[{"id":"https://openalex.org/I145372079","display_name":"Instituto Tecnol\u00f3gico de Costa Rica","ror":"https://ror.org/04zhrfn38","country_code":"CR","type":"education","lineage":["https://openalex.org/I145372079"]}],"countries":["CR"],"is_corresponding":true,"raw_author_name":"Carlos Salazar-Garcia","raw_affiliation_strings":["Instituto Tecnologico de Costa Rica, Cartago, Costa Rica"],"affiliations":[{"raw_affiliation_string":"Instituto Tecnologico de Costa Rica, Cartago, Costa Rica","institution_ids":["https://openalex.org/I145372079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085541149","display_name":"Ronny Garc\u00eda-Ram\u00edrez","orcid":"https://orcid.org/0000-0002-6225-2882"},"institutions":[{"id":"https://openalex.org/I145372079","display_name":"Instituto Tecnol\u00f3gico de Costa Rica","ror":"https://ror.org/04zhrfn38","country_code":"CR","type":"education","lineage":["https://openalex.org/I145372079"]}],"countries":["CR"],"is_corresponding":false,"raw_author_name":"Ronny Garcia-Ramirez","raw_affiliation_strings":["Instituto Tecnologico de Costa Rica, Cartago, Costa Rica"],"affiliations":[{"raw_affiliation_string":"Instituto Tecnologico de Costa Rica, Cartago, Costa Rica","institution_ids":["https://openalex.org/I145372079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016276572","display_name":"Renato R\u00edmolo-Donad\u00edo","orcid":"https://orcid.org/0000-0002-3087-9162"},"institutions":[{"id":"https://openalex.org/I145372079","display_name":"Instituto Tecnol\u00f3gico de Costa Rica","ror":"https://ror.org/04zhrfn38","country_code":"CR","type":"education","lineage":["https://openalex.org/I145372079"]}],"countries":["CR"],"is_corresponding":false,"raw_author_name":"Renato Rimolo-Donadio","raw_affiliation_strings":["Instituto Tecnol\u00f3gico de Costa Rica, Cartago, Costa Rica"],"affiliations":[{"raw_affiliation_string":"Instituto Tecnol\u00f3gico de Costa Rica, Cartago, Costa Rica","institution_ids":["https://openalex.org/I145372079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077785373","display_name":"Christos Strydis","orcid":"https://orcid.org/0000-0002-0935-9322"},"institutions":[{"id":"https://openalex.org/I2801952686","display_name":"Erasmus MC","ror":"https://ror.org/018906e22","country_code":"NL","type":"funder","lineage":["https://openalex.org/I2801952686"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Christos Strydis","raw_affiliation_strings":["Dept. of Neuroscience, Erasmus Medical Center, Rotterdam, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Dept. of Neuroscience, Erasmus Medical Center, Rotterdam, The Netherlands","institution_ids":["https://openalex.org/I2801952686"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008926764","display_name":"Alfonso Chac\u00f3n-Rodr\u00edguez","orcid":"https://orcid.org/0000-0002-9094-8983"},"institutions":[{"id":"https://openalex.org/I145372079","display_name":"Instituto Tecnol\u00f3gico de Costa Rica","ror":"https://ror.org/04zhrfn38","country_code":"CR","type":"education","lineage":["https://openalex.org/I145372079"]}],"countries":["CR"],"is_corresponding":false,"raw_author_name":"Alfonso Chacon-Rodriguez","raw_affiliation_strings":["Instituto Tecnologico de Costa Rica, Cartago, Costa Rica"],"affiliations":[{"raw_affiliation_string":"Instituto Tecnologico de Costa Rica, Cartago, Costa Rica","institution_ids":["https://openalex.org/I145372079"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5061035642"],"corresponding_institution_ids":["https://openalex.org/I145372079"],"apc_list":null,"apc_paid":null,"fwci":0.4062,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.59826767,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9046996831893921},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.8692985773086548},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7818199992179871},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.687896192073822},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6689193248748779},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6470013856887817},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6068775653839111},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.5333794355392456},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5280207991600037},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44873106479644775},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4329472482204437},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37324249744415283},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20111286640167236},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13236957788467407},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.06225124001502991}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9046996831893921},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.8692985773086548},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7818199992179871},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.687896192073822},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6689193248748779},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6470013856887817},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6068775653839111},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.5333794355392456},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5280207991600037},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44873106479644775},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4329472482204437},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37324249744415283},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20111286640167236},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13236957788467407},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.06225124001502991},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas51556.2021.9401058","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas51556.2021.9401058","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:eur:oai:pure.eur.nl:publications/541bef30-27af-494f-9e05-6d0411d903d4","is_oa":false,"landing_page_url":"https://pure.eur.nl/en/publications/541bef30-27af-494f-9e05-6d0411d903d4","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings, 1 - 5","raw_type":"info:eu-repo/semantics/conferencepaper"},{"id":"pmh:oai:pure.eur.nl:publications/541bef30-27af-494f-9e05-6d0411d903d4","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=85108994627&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306401266","display_name":"EUR Research Repository (Erasmus University Rotterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I913958620","host_organization_name":"Erasmus University Rotterdam","host_organization_lineage":["https://openalex.org/I913958620"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Salazar-Garc\u00eda , C , Garc\u00eda-Ram\u00edrez , R , R\u00edmolo-Donad\u00edo , R , Strydis , C & Chac\u00f3n-Rodr\u00edguez , A 2021 , PlasticNet+ : Extending multi-FPGA interconnect architecture via Gigabit transceivers . in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings . , 9401058 , Institute of Electrical and Electronics Engineers Inc. , Proceedings - IEEE International Symposium on Circuits and Systems , vol. 2021-May , pp. 1-5 , 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 , Daegu , Korea, Republic of , 22/05/21 . https://doi.org/10.1109/ISCAS51556.2021.9401058","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1485095763","https://openalex.org/W1553214226","https://openalex.org/W1979246114","https://openalex.org/W2021295531","https://openalex.org/W2025347051","https://openalex.org/W2050160581","https://openalex.org/W2087384518","https://openalex.org/W2114691690","https://openalex.org/W2115002670","https://openalex.org/W2116433835","https://openalex.org/W2516125595","https://openalex.org/W2764043525","https://openalex.org/W2789250549","https://openalex.org/W2922361944","https://openalex.org/W3015794818","https://openalex.org/W3016050587","https://openalex.org/W4229635340","https://openalex.org/W4235054035"],"related_works":["https://openalex.org/W1989703526","https://openalex.org/W2169580068","https://openalex.org/W2054088497","https://openalex.org/W2798426149","https://openalex.org/W2393701163","https://openalex.org/W4232546846","https://openalex.org/W2011081932","https://openalex.org/W2387382509","https://openalex.org/W2116209852","https://openalex.org/W2166633816"],"abstract_inverted_index":{"This":[0,89],"paper":[1],"addresses":[2],"the":[3,18,33,39,68,74,81,91,98],"communication":[4],"challenges":[5],"posed":[6],"in":[7,22,43,60],"multi-FPGA":[8,103],"systems,":[9],"by":[10],"improving":[11],"a":[12,50,65,94],"custom":[13],"FPGA":[14,24,46],"interconnect":[15],"architecture":[16],"via":[17],"high-speed":[19,40],"transceivers":[20],"available":[21],"modern":[23],"development":[25,99],"boards.":[26,47],"The":[27],"proposed":[28],"network":[29,86],"interconnection,":[30],"built":[31],"upon":[32],"PlasticNet":[34],"architecture,":[35],"is":[36],"evaluated":[37],"using":[38],"serial":[41],"transceiver":[42],"Zynq":[44],"ZC706":[45],"Results":[48],"show":[49],"best-case":[51],"latency":[52,63],"of":[53,62,76,84,100],"only":[54],"300":[55],"ns,":[56],"demonstrating":[57],"equivalent":[58],"results":[59],"terms":[61],"on":[64],"par":[66],"with":[67,73],"known":[69],"BlueLink":[70],"framework,":[71],"but":[72],"plus":[75],"having":[77],"total":[78],"re-configurability":[79],"across":[80],"different":[82],"layers":[83],"its":[85],"interconnection":[87],"model.":[88],"makes":[90],"current":[92],"proposal":[93],"competitive":[95],"option":[96],"for":[97],"distributed,":[101],"heterogeneous":[102],"processing":[104],"systems.":[105]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}