{"id":"https://openalex.org/W4313162869","doi":"https://doi.org/10.1109/iscas48785.2022.9937877","title":"Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer","display_name":"Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4313162869","doi":"https://doi.org/10.1109/iscas48785.2022.9937877"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937877","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036685018","display_name":"Ragh Kuttappa","orcid":"https://orcid.org/0000-0003-1022-2187"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ragh Kuttappa","raw_affiliation_strings":["Drexel University,Philadelphia,PA,USA","Drexel University, Philadelphia, PA, USA"],"affiliations":[{"raw_affiliation_string":"Drexel University,Philadelphia,PA,USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Drexel University,Philadelphia,PA,USA","Drexel University, Philadelphia, PA, USA"],"affiliations":[{"raw_affiliation_string":"Drexel University,Philadelphia,PA,USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072530511","display_name":"Vinayak Honkote","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinayak Honkote","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024748519","display_name":"Satish Yada","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Yada","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084364715","display_name":"Jainaveen Sundaram","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jainaveen Sundaram","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080985621","display_name":"Dileep Kurian","orcid":"https://orcid.org/0009-0000-9348-8348"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dileep Kurian","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016416631","display_name":"Tanay Karnik","orcid":"https://orcid.org/0000-0003-0072-1492"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanay Karnik","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013164342","display_name":"Anuradha Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anuradha Srinivasan","raw_affiliation_strings":["Intel Labs, OR,USA","Intel Labs, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5036685018"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":0.6445,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63255281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"692","last_page":"696"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.875273585319519},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6510685086250305},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6112310290336609},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5952630043029785},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.577429473400116},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.524868905544281},{"id":"https://openalex.org/keywords/oscillation","display_name":"Oscillation (cell signaling)","score":0.5127171277999878},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5030021071434021},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4838032126426697},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4655284285545349},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.46447670459747314},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4424419403076172},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.36172735691070557},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3358227014541626},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3352031707763672},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.2732239365577698},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10397782921791077},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09507736563682556}],"concepts":[{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.875273585319519},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6510685086250305},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6112310290336609},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5952630043029785},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.577429473400116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.524868905544281},{"id":"https://openalex.org/C2778439541","wikidata":"https://www.wikidata.org/wiki/Q7106412","display_name":"Oscillation (cell signaling)","level":2,"score":0.5127171277999878},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5030021071434021},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4838032126426697},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4655284285545349},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.46447670459747314},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4424419403076172},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.36172735691070557},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3358227014541626},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3352031707763672},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2732239365577698},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10397782921791077},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09507736563682556},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C100460472","wikidata":"https://www.wikidata.org/wiki/Q2368605","display_name":"Etching (microfabrication)","level":3,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937877","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2034822545","https://openalex.org/W2055990800","https://openalex.org/W2119160089","https://openalex.org/W2122724421","https://openalex.org/W2234584938","https://openalex.org/W2290936236","https://openalex.org/W2518432791","https://openalex.org/W2625200202","https://openalex.org/W2799472237","https://openalex.org/W2802000047","https://openalex.org/W2918847811","https://openalex.org/W2971909604","https://openalex.org/W2977415399","https://openalex.org/W2980104813","https://openalex.org/W3002319033","https://openalex.org/W3015587302","https://openalex.org/W3111684448","https://openalex.org/W3132197712","https://openalex.org/W4240214568","https://openalex.org/W4244395536"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W4386968318","https://openalex.org/W1506442459","https://openalex.org/W2169622190","https://openalex.org/W2090237663","https://openalex.org/W2174922170","https://openalex.org/W2122646466","https://openalex.org/W853533475","https://openalex.org/W2147595938","https://openalex.org/W331180034"],"abstract_inverted_index":{"Rotary":[0],"traveling":[1],"wave":[2],"oscillators":[3],"(RTWO)":[4],"are":[5,33,47,81],"designed":[6],"to":[7,18],"provide":[8],"a":[9,22,50,54,72],"high":[10],"frequency":[11,74],"clock":[12,73,84],"signal":[13],"through":[14],"the":[15,98],"silicon":[16,51],"interposer":[17,37,42,52],"multiple":[19],"chiplets":[20],"in":[21],"heterogeneous":[23],"2.5D":[24],"system.":[25],"In":[26],"particular,":[27],"two":[28],"different":[29],"RTWO":[30,38],"synchronization":[31],"topologies":[32,46],"presented:":[34],"1)":[35],"Active":[36],"and":[39,91,94],"2)":[40],"passive":[41],"RTWO.":[43],"The":[44,78],"proposed":[45],"evaluated":[48],"across":[49,97],"with":[53,66,102],"dimension":[55],"of":[56,75],"42":[57],"mm":[58],"\u00d7":[59],"20":[60],"mm.":[61],"Each":[62],"topology":[63],"is":[64],"implemented":[65],"post-layout,":[67],"parasitic":[68],"extracted":[69],"models":[70],"for":[71,83],"\u22488":[76],"GHz.":[77],"performance":[79],"metrics":[80],"presented":[82],"period,":[85],"skew,":[86],"rise":[87],"time,":[88,90],"fall":[89],"oscillation":[92],"start-up":[93],"settling":[95],"times":[96],"multi-die":[99],"system":[100],"(MDS)":[101],"SPICE":[103],"based":[104],"simulations.":[105]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
