{"id":"https://openalex.org/W4312445232","doi":"https://doi.org/10.1109/iscas48785.2022.9937841","title":"A Hybrid Memristor/CMOS SNN for Implementing One-Shot Winner-Takes-All Training","display_name":"A Hybrid Memristor/CMOS SNN for Implementing One-Shot Winner-Takes-All Training","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4312445232","doi":"https://doi.org/10.1109/iscas48785.2022.9937841"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937841","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007956016","display_name":"Javad Ahmadi-Farsani","orcid":null},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Javad Ahmadi-Farsani","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070455875","display_name":"Saverio Ricci","orcid":"https://orcid.org/0000-0003-0806-5020"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Saverio Ricci","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000848957","display_name":"Shahin Hashemkhani","orcid":"https://orcid.org/0000-0003-3629-6424"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Shahin Hashemkhani","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054173368","display_name":"Daniele Ielmini","orcid":"https://orcid.org/0000-0002-1853-1614"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Daniele Ielmini","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla, CSIC/Universidad de Sevilla,Sevilla,Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025922642","display_name":"B. Linares-Barranco","orcid":"https://orcid.org/0000-0002-1813-4889"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Bernabe Linares-Barranco","raw_affiliation_strings":["Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria,Milan,Italy","Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria,Milan,Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079540787","display_name":"Teresa Serrano\u2010Gotarredona","orcid":"https://orcid.org/0000-0001-5714-2526"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Teresa Serrano-Gotarredona","raw_affiliation_strings":["Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria,Milan,Italy","Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria,Milan,Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5007956016"],"corresponding_institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.22150411,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"210","last_page":"214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7553660273551941},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7023698091506958},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.685748279094696},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6446820497512817},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6421267986297607},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.580115795135498},{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.4760051667690277},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4191398620605469},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.37951648235321045},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3658287525177002},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3542459011077881},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.29360777139663696},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25086528062820435},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16576924920082092},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09847983717918396}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7553660273551941},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7023698091506958},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.685748279094696},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6446820497512817},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6421267986297607},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.580115795135498},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.4760051667690277},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4191398620605469},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.37951648235321045},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3658287525177002},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3542459011077881},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.29360777139663696},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25086528062820435},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16576924920082092},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09847983717918396}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937841","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1227859","is_oa":false,"landing_page_url":"https://hdl.handle.net/11311/1227859","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320324211","display_name":"Ministry of Economy","ror":"https://ror.org/02fn8ac40"},{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1975398991","https://openalex.org/W2018240811","https://openalex.org/W2051736202","https://openalex.org/W2129788035","https://openalex.org/W2152323008","https://openalex.org/W2154326304","https://openalex.org/W2156640153","https://openalex.org/W2525649597","https://openalex.org/W2532666972","https://openalex.org/W2883593518","https://openalex.org/W2890584292","https://openalex.org/W3003821665","https://openalex.org/W3080915835","https://openalex.org/W3113676811","https://openalex.org/W6663196874","https://openalex.org/W6679148083"],"related_works":["https://openalex.org/W1872623660","https://openalex.org/W3207218810","https://openalex.org/W4292697011","https://openalex.org/W3212508523","https://openalex.org/W1995352804","https://openalex.org/W4386475142","https://openalex.org/W2909534142","https://openalex.org/W2086672837","https://openalex.org/W2793181810","https://openalex.org/W4367187682"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,25,45,51,105,110],"spiking":[4],"neural":[5],"network":[6,11,113],"for":[7],"pattern":[8],"recognition.":[9],"The":[10,60,77],"synapses":[12],"are":[13,24,35],"realized":[14],"by":[15],"resistive":[16],"switching":[17],"random":[18],"access":[19],"memory":[20],"(ReRAM)":[21],"cells,":[22],"which":[23],"stack":[26],"of":[27,40],"Au/Ti/C/Ti/HfO":[28],"<inf":[29],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[30],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>":[31],"/Pt.":[32],"These":[33],"cells":[34],"connected":[36],"to":[37,49,66,73,89,92,120],"an":[38],"array":[39],"NMOS":[41],"transistors":[42],"(fabricated":[43],"in":[44,104,125],"CMOS":[46,106],"180nm":[47,107],"technology)":[48],"form":[50],"4by4":[52],"1T1R":[53],"crossbar":[54],"between":[55],"pre":[56],"and":[57],"postsynaptic":[58],"circuitries.":[59],"pre-synaptic":[61],"part":[62],"contains":[63],"conditioning":[64],"circuits":[65,102],"reshape":[67],"the":[68,74,85,112],"inputs":[69],"before":[70],"applying":[71],"them":[72],"memristive":[75],"crossbar.":[76],"post-synaptic":[78],"section":[79],"includes":[80],"current":[81],"attenuators":[82],"that":[83],"allowed":[84],"memristor":[86],"domain":[87,94],"currents":[88],"be":[90],"mapped":[91],"neuron":[93,101],"currents,":[95],"as":[96,98],"well":[97],"physiologically":[99],"realistic":[100],"fabricated":[103],"technology.":[108],"As":[109],"demonstrator,":[111],"is":[114],"trained":[115],"with":[116],"one-shot":[117],"winner-takes-all":[118],"method":[119],"differentiate":[121],"four":[122],"input":[123],"patterns":[124],"its":[126],"inference":[127],"mode.":[128]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
