{"id":"https://openalex.org/W4312592863","doi":"https://doi.org/10.1109/iscas48785.2022.9937727","title":"An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells","display_name":"An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4312592863","doi":"https://doi.org/10.1109/iscas48785.2022.9937727"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937727","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937727","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050097039","display_name":"Xiaole Cui","orcid":"https://orcid.org/0000-0002-3382-3703"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I4210136793","display_name":"Peng Cheng Laboratory","ror":"https://ror.org/03qdqbt06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210136793"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaole Cui","raw_affiliation_strings":["Institute of Microelectronics, Peking University,Beijing,China,100871","Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","Peng Cheng Lab, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University,Beijing,China,100871","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Peng Cheng Lab, Shenzhen, China","institution_ids":["https://openalex.org/I4210136793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100371038","display_name":"Fan Liu","orcid":"https://orcid.org/0000-0002-5299-9317"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210136793","display_name":"Peng Cheng Laboratory","ror":"https://ror.org/03qdqbt06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210136793"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Liu","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","Peng Cheng Lab, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Peng Cheng Lab, Shenzhen, China","institution_ids":["https://openalex.org/I4210136793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062370793","display_name":"Sunrui Zhang","orcid":"https://orcid.org/0009-0000-9539-1427"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sunrui Zhang","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055"],"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048410928","display_name":"Xiaoxin Cui","orcid":"https://orcid.org/0000-0002-0394-8839"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoxin Cui","raw_affiliation_strings":["Institute of Microelectronics, Peking University,Beijing,China,100871","Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University,Beijing,China,100871","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China,518055","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5050097039"],"corresponding_institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392","https://openalex.org/I4210136793"],"apc_list":null,"apc_paid":null,"fwci":0.6445,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.6211233,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"2571","last_page":"2575"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8901361227035522},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8076770305633545},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.67582768201828},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5613336563110352},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4937354028224945},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44683837890625},{"id":"https://openalex.org/keywords/resistive-touchscreen","display_name":"Resistive touchscreen","score":0.41667911410331726},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37778544425964355},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33257433772087097},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32384878396987915},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28773242235183716},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2565386891365051},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18114247918128967},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11753523349761963}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8901361227035522},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8076770305633545},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.67582768201828},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5613336563110352},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4937354028224945},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44683837890625},{"id":"https://openalex.org/C6899612","wikidata":"https://www.wikidata.org/wiki/Q852911","display_name":"Resistive touchscreen","level":2,"score":0.41667911410331726},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37778544425964355},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33257433772087097},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32384878396987915},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28773242235183716},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2565386891365051},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18114247918128967},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11753523349761963},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937727","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937727","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1905680397","https://openalex.org/W1967035245","https://openalex.org/W2010160963","https://openalex.org/W2016306973","https://openalex.org/W2024203951","https://openalex.org/W2056251131","https://openalex.org/W2099554009","https://openalex.org/W2112181056","https://openalex.org/W2585439909","https://openalex.org/W2595197904","https://openalex.org/W2738894409","https://openalex.org/W2967617888","https://openalex.org/W3023788148","https://openalex.org/W4214686615","https://openalex.org/W6681989696"],"related_works":["https://openalex.org/W2545245183","https://openalex.org/W2054635671","https://openalex.org/W2017425642","https://openalex.org/W2350916061","https://openalex.org/W1970117475","https://openalex.org/W4396815615","https://openalex.org/W3161624601","https://openalex.org/W2078381924","https://openalex.org/W2199653281","https://openalex.org/W2128242959"],"abstract_inverted_index":{"The":[0,19,67,89],"resistive":[1],"random":[2],"access":[3],"memory":[4],"(RRAM)":[5],"is":[6,75],"a":[7,51],"two-terminal":[8],"device,":[9],"which":[10],"represents":[11],"logic":[12,36,60],"states":[13],"with":[14],"its":[15],"different":[16],"resistance":[17,42],"states.":[18],"RRAM":[20,34,46],"devices":[21],"were":[22],"applied":[23,76],"to":[24,63,77],"the":[25,33,41,45,57,72,79,85,96,101,106],"Look-Up":[26],"Table":[27],"(LUT)":[28],"in":[29],"recent":[30],"years.":[31],"However,":[32],"based":[35,55],"circuits":[37],"are":[38],"affected":[39],"by":[40],"variation":[43],"of":[44,71,81,84],"devices.":[47],"This":[48],"work":[49],"proposes":[50],"memristive":[52],"LUT":[53,87,98,108],"scheme":[54,99],"on":[56],"enhanced":[58],"scouting":[59],"(ESL)":[61],"cells,":[62],"address":[64],"this":[65],"challenge.":[66],"read-write":[68],"separation":[69],"feature":[70],"ESL":[73],"cell":[74],"reduce":[78],"number":[80],"working":[82],"cycles":[83],"proposed":[86,97,107],"circuit.":[88],"Monte":[90],"Carlo":[91],"simulation":[92],"results":[93],"show":[94],"that":[95],"has":[100,109],"small":[102,111],"standard":[103],"deviation.":[104],"And":[105],"relatively":[110],"area":[112],"and":[113],"high":[114],"performance.":[115]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}