{"id":"https://openalex.org/W4312386704","doi":"https://doi.org/10.1109/iscas48785.2022.9937493","title":"Modernizing Hardware Circuits through High-Level Synthesis","display_name":"Modernizing Hardware Circuits through High-Level Synthesis","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4312386704","doi":"https://doi.org/10.1109/iscas48785.2022.9937493"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937493","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026339104","display_name":"Md Imtiaz Rashid","orcid":"https://orcid.org/0000-0003-2144-181X"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Md Imtiaz Rashid","raw_affiliation_strings":["The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000234588","display_name":"Qilin Si","orcid":"https://orcid.org/0009-0005-2885-7553"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qilin Si","raw_affiliation_strings":["The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":null,"display_name":"Benjamin Carrion Schaefer","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benjamin Carrion Schaefer","raw_affiliation_strings":["The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Dallas,Department of Electrical and Computer Engineering,TX,USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5026339104"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.4275,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.49297189,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1739","last_page":"1743"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7837711572647095},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7393498420715332},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7152798771858215},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6778869032859802},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5736105442047119},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.5354822874069214},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5297858715057373},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.529051661491394},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.49769023060798645},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4872068762779236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46710649132728577},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.45445939898490906},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.430942565202713},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.40733271837234497},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3870532512664795},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3526346683502197},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3143598437309265},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.19513878226280212},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17717820405960083}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7837711572647095},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7393498420715332},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7152798771858215},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6778869032859802},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5736105442047119},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.5354822874069214},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5297858715057373},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.529051661491394},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.49769023060798645},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4872068762779236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46710649132728577},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.45445939898490906},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.430942565202713},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.40733271837234497},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3870532512664795},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3526346683502197},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3143598437309265},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.19513878226280212},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17717820405960083},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937493","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2028177656","https://openalex.org/W2048795179","https://openalex.org/W2075051717","https://openalex.org/W2888324132","https://openalex.org/W2943018402","https://openalex.org/W2945560322","https://openalex.org/W2975468520","https://openalex.org/W3089476745","https://openalex.org/W3158956772","https://openalex.org/W4211236386"],"related_works":["https://openalex.org/W1547989843","https://openalex.org/W1843355381","https://openalex.org/W2537479781","https://openalex.org/W2157905069","https://openalex.org/W2916312349","https://openalex.org/W2168152852","https://openalex.org/W2120819183","https://openalex.org/W4312386704","https://openalex.org/W2618316163","https://openalex.org/W2076487538"],"abstract_inverted_index":{"This":[0,51],"works":[1],"presents":[2],"a":[3,150,158,182],"design":[4],"methodology":[5,25],"to":[6,31,45,86,111,114],"reoptimize":[7],"legacy":[8],"Register-Transfer":[9],"level":[10],"(RTL)":[11],"designs":[12],"specified":[13],"in":[14,84,101],"synthesizable":[15,36],"Verilog":[16],"or":[17,104,125,134,143],"VHDL":[18],"through":[19],"High-Level":[20],"Synthesis":[21],"(HLS).":[22],"The":[23],"proposed":[24,194],"is":[26,69,81],"based":[27],"on":[28],"an":[29],"RTL":[30,37,61],"C":[32],"compiler":[33],"that":[34,68,72,107,157],"converts":[35],"descriptions":[38,43],"into":[39,137],"functional":[40],"equivalent":[41,71],"behavioral":[42],"optimized":[44],"maximize":[46,87],"its":[47],"re-usability":[48],"though":[49],"HLS.":[50],"implies":[52],"stripping":[53],"off":[54],"all":[55],"the":[56,60,88,102,175,190],"timing":[57],"information":[58],"from":[59,174,186],"description":[62],"and":[63,76,140,168],"generating":[64,146],"only":[65],"C/C++":[66,147,177],"code":[67,148],"functionally":[70],"has":[73],"arrays,":[74],"loops":[75,118],"functions.":[77],"Generating":[78],"these":[79,154],"structures":[80,155],"very":[82],"important":[83],"order":[85],"re-optimization":[89],"potential":[90],"as":[91,131],"commercial":[92],"HLS":[93,109],"tools":[94],"make":[95],"extensive":[96],"use":[97],"of":[98,153,184,192],"synthesis":[99],"directives":[100],"form":[103],"pragmas":[105],"(comments)":[106],"allow":[108],"users":[110],"control":[112],"how":[113],"synthesize":[115],"them.":[116],"E.g.,":[117],"can":[119,128,171],"be":[120,129,172],"fully":[121,135],"unrolled,":[122],"partially":[123],"unrolled":[124],"pipelined,":[126],"arrays":[127],"synthesized":[130],"registers,":[132],"memories":[133],"expanded":[136],"individual":[138],"flip-flops":[139],"functions":[141],"inline":[142],"not.":[144],"Thus,":[145],"with":[149,163,181],"larger":[151,159],"number":[152],"ensures":[156],"variety":[160,183],"unique":[161],"implementations":[162],"different":[164,187],"area":[165],"vs.":[166],"performance":[167],"power":[169],"trade-offs":[170],"generated":[173],"converted":[176],"code.":[178],"Experimental":[179],"results":[180],"applications":[185],"domains":[188],"show":[189],"effectiveness":[191],"your":[193],"flow.":[195]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
