{"id":"https://openalex.org/W4312632053","doi":"https://doi.org/10.1109/iscas48785.2022.9937426","title":"Implementation of High Performance IEEE 754-Posit Conversion Hardware","display_name":"Implementation of High Performance IEEE 754-Posit Conversion Hardware","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4312632053","doi":"https://doi.org/10.1109/iscas48785.2022.9937426"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937426","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937426","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048421422","display_name":"Brett Mathis","orcid":null},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brett Mathis","raw_affiliation_strings":["Oklahoma State University,VLSI Computer Architecture Research Group School of Electrical and Computer Engineering,Stillwater,Oklahoma,USA,74078"],"affiliations":[{"raw_affiliation_string":"Oklahoma State University,VLSI Computer Architecture Research Group School of Electrical and Computer Engineering,Stillwater,Oklahoma,USA,74078","institution_ids":["https://openalex.org/I115475287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033770307","display_name":"James E. Stine","orcid":"https://orcid.org/0000-0001-8767-390X"},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James E. Stine","raw_affiliation_strings":["Oklahoma State University,VLSI Computer Architecture Research Group School of Electrical and Computer Engineering,Stillwater,Oklahoma,USA,74078"],"affiliations":[{"raw_affiliation_string":"Oklahoma State University,VLSI Computer Architecture Research Group School of Electrical and Computer Engineering,Stillwater,Oklahoma,USA,74078","institution_ids":["https://openalex.org/I115475287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048421422"],"corresponding_institution_ids":["https://openalex.org/I115475287"],"apc_list":null,"apc_paid":null,"fwci":0.518,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57508251,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"934","last_page":"937"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7497455477714539},{"id":"https://openalex.org/keywords/ieee-floating-point","display_name":"IEEE floating point","score":0.6891409754753113},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.6088557243347168},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5570296049118042},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5134885907173157},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4562382400035858},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.4330673813819885},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39582639932632446},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.3263821601867676},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25274431705474854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23601770401000977}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7497455477714539},{"id":"https://openalex.org/C137231763","wikidata":"https://www.wikidata.org/wiki/Q828287","display_name":"IEEE floating point","level":3,"score":0.6891409754753113},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.6088557243347168},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5570296049118042},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5134885907173157},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4562382400035858},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.4330673813819885},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39582639932632446},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.3263821601867676},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25274431705474854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23601770401000977},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937426","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937426","pdf_url":null,"source":{"id":"https://openalex.org/S4363604393","display_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1582324226","https://openalex.org/W2142917159","https://openalex.org/W2207050309","https://openalex.org/W2743322459","https://openalex.org/W2908782257","https://openalex.org/W2948396960","https://openalex.org/W2955474694","https://openalex.org/W2989610989","https://openalex.org/W3043484776","https://openalex.org/W6742278618"],"related_works":["https://openalex.org/W2596474508","https://openalex.org/W2037018251","https://openalex.org/W4232549588","https://openalex.org/W3193325075","https://openalex.org/W2797902698","https://openalex.org/W3133934505","https://openalex.org/W1573821047","https://openalex.org/W2571248630","https://openalex.org/W2074888833","https://openalex.org/W2544512391"],"abstract_inverted_index":{"This":[0],"paper":[1],"demonstrates":[2],"the":[3,12,28,32,42,47],"implementation":[4],"of":[5,49],"conversion":[6,30,40],"hardware":[7],"between":[8,41],"floating-point":[9],"operands":[10],"in":[11,19,77,82,110],"standardized":[13],"IEEE":[14,36,53,99],"754":[15,54,100],"format":[16,34],"to":[17,35,66,79,91],"those":[18],"a":[20],"Posit":[21,33,56,105],"type-III":[22],"unum":[23],"format,":[24],"as":[25,27],"well":[26],"reverse":[29],"from":[31],"754.":[37],"High":[38,70],"performance":[39,87],"two":[43],"standards":[44],"will":[45],"encourage":[46],"use":[48],"dual-mode":[50],"systems":[51],"where":[52],"and":[55,102,117],"architectures":[57,94],"can":[58],"be":[59],"used":[60],"interchangeably":[61],"when":[62],"they":[63],"are":[64,95,108],"advantageous":[65],"each":[67],"other,":[68],"respectively.":[69],"performance,":[71],"structural":[72],"RTL":[73],"architecture":[74,81],"is":[75],"shown":[76,96],"comparison":[78],"behavioral":[80,93],"existing":[83,92],"literature,":[84],"yielding":[85],"significant":[86],"improvements.":[88],"Synthesis":[89],"comparisons":[90],"for":[97],"standard":[98],"precisions":[101],"their":[103],"closest":[104],"analogues.":[106],"Results":[107],"given":[109],"cmos32soi32nm":[111],"MTCMOS":[112],"technology":[113],"using":[114],"ARM-based":[115],"standard-cells":[116],"commercial":[118],"EDA":[119],"toolsets.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-01-13T01:12:25.745995","created_date":"2025-10-10T00:00:00"}
