{"id":"https://openalex.org/W4312825221","doi":"https://doi.org/10.1109/iscas48785.2022.9937329","title":"Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing","display_name":"Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing","publication_year":2022,"publication_date":"2022-05-28","ids":{"openalex":"https://openalex.org/W4312825221","doi":"https://doi.org/10.1109/iscas48785.2022.9937329"},"language":"en","primary_location":{"id":"doi:10.1109/iscas48785.2022.9937329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101855878","display_name":"Shubham Kumar","orcid":"https://orcid.org/0000-0003-4228-9802"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shubham Kumar","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083027686","display_name":"Swetaki Chatterjee","orcid":"https://orcid.org/0000-0002-2550-9626"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Swetaki Chatterjee","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066470105","display_name":"Chetan Kumar Dabhi","orcid":"https://orcid.org/0000-0003-0795-4598"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chetan Kumar Dabhi","raw_affiliation_strings":["University of California,Electrical Engineering Department,Berkely,CA,USA,94720"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Electrical Engineering Department,Berkely,CA,USA,94720","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hussam Amrouch","orcid":null},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hussam Amrouch","raw_affiliation_strings":["University of Stuttgart,Chair of Semiconductor Test and Reliability (STAR),Stuttgart,Germany","Chair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Stuttgart,Chair of Semiconductor Test and Reliability (STAR),Stuttgart,Germany","institution_ids":["https://openalex.org/I100066346"]},{"raw_affiliation_string":"Chair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077371510","display_name":"Yogesh Singh Chauhan","orcid":"https://orcid.org/0000-0002-3356-8917"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Yogesh Singh Chauhan","raw_affiliation_strings":["Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kanpur,Electrical Engineering Department,Kanpur,India,208016","institution_ids":["https://openalex.org/I94234084"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.1301,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.9584186,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"3373","last_page":"3377"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.9784618020057678},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5646262764930725},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5128400921821594},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49930834770202637},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.46478912234306335},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3582070469856262},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3017776608467102},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.24719932675361633},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24535876512527466},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19162282347679138}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.9784618020057678},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5646262764930725},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5128400921821594},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49930834770202637},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.46478912234306335},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3582070469856262},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3017776608467102},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.24719932675361633},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24535876512527466},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19162282347679138}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas48785.2022.9937329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas48785.2022.9937329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1994627436","https://openalex.org/W2001971725","https://openalex.org/W2017926762","https://openalex.org/W2108719777","https://openalex.org/W2108971405","https://openalex.org/W2120050065","https://openalex.org/W2140092109","https://openalex.org/W2140863609","https://openalex.org/W2154763313","https://openalex.org/W3000301330","https://openalex.org/W3016940091","https://openalex.org/W3030383331","https://openalex.org/W3035768999","https://openalex.org/W3103339143","https://openalex.org/W3121649706","https://openalex.org/W6676544959"],"related_works":["https://openalex.org/W4385413421","https://openalex.org/W4386414224","https://openalex.org/W2963244787","https://openalex.org/W2783592119","https://openalex.org/W2774773774","https://openalex.org/W2785627314","https://openalex.org/W1963739940","https://openalex.org/W2069684819","https://openalex.org/W1908137878","https://openalex.org/W4252086118"],"abstract_inverted_index":{"For":[0],"the":[1,35,48,70,90,94,118,125,130,138,142,148],"first":[2],"time,":[3],"we":[4,136],"propose":[5],"a":[6,61],"novel":[7,66,111],"circuit":[8],"for":[9],"dynamic":[10,84,132],"2-input":[11],"XNOR":[12,67,85,112,133,152],"gate":[13,56],"that":[14,109],"merely":[15],"employs":[16],"two":[17],"n-type":[18],"Fully-Depleted":[19],"Silicon":[20],"on":[21,147],"Insulator":[22],"(nFDSOI)":[23],"FETs":[24],"along":[25],"with":[26],"one":[27,52],"additional":[28],"precharging":[29],"pFDSOI":[30],"FET.":[31],"Our":[32],"design":[33,68],"exploits":[34],"threshold":[36],"voltage":[37],"(Vt)":[38],"tuning":[39],"feature":[40],"(i.e.,":[41],"1ow-Vtand":[42],"high-Vtstates)":[43],"of":[44,72,92,141,150],"FDSOI":[45],"FET":[46],"using":[47],"back":[49],"bias":[50,57],"as":[51,60],"input.":[53,63],"The":[54,64,106],"front":[55],"is":[58],"used":[59],"second":[62],"proposed":[65,151],"reduces":[69,76],"number":[71],"transistors":[73],"and":[74,79,121],"significantly":[75],"power,":[77],"delay,":[78],"energy":[80],"compared":[81,128],"to":[82,129],"state-of-the-art":[83,131],"gates.":[86],"To":[87],"accurately":[88],"evaluate":[89],"Figure":[91],"merits,":[93],"industrial":[95,104],"transistor":[96],"compact":[97],"model":[98],"has":[99],"been":[100],"carefully":[101],"calibrated":[102],"against":[103],"measurements.":[105],"analysis":[107],"demonstrates":[108],"our":[110],"gates":[113],"exhibits":[114],"$8\\times$":[115],"improvement":[116,123],"in":[117,124],"propagation":[119],"delay":[120],"$17\\times$":[122],"power":[126],"consumption":[127],"design.":[134,153],"Additionally,":[135],"explore":[137],"critical":[139],"role":[140],"buried":[143],"oxide":[144],"(BOX)":[145],"thickness":[146],"performance":[149]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}