{"id":"https://openalex.org/W4385080176","doi":"https://doi.org/10.1109/iscas46773.2023.10182079","title":"System on Chip Testbed for Deep Neuromorphic Neural Networks","display_name":"System on Chip Testbed for Deep Neuromorphic Neural Networks","publication_year":2023,"publication_date":"2023-05-21","ids":{"openalex":"https://openalex.org/W4385080176","doi":"https://doi.org/10.1109/iscas46773.2023.10182079"},"language":"en","primary_location":{"id":"doi:10.1109/iscas46773.2023.10182079","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10182079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002460040","display_name":"Nicol\u00e1s Rodr\u00edguez","orcid":"https://orcid.org/0000-0002-9290-7894"},"institutions":[{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Nicol\u00e1s Rodr\u00edguez","raw_affiliation_strings":["Silicon Austria Labs,Linz,Austria","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Austria Labs,Linz,Austria","institution_ids":["https://openalex.org/I4210123126"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031974536","display_name":"Mart\u00edn Villemur","orcid":"https://orcid.org/0000-0001-8385-9758"},"institutions":[{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Mart\u00edn Villemur","raw_affiliation_strings":["Silicon Austria Labs,Linz,Austria","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Austria Labs,Linz,Austria","institution_ids":["https://openalex.org/I4210123126"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019201655","display_name":"Daniel Klepatsch","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Daniel Klepatsch","raw_affiliation_strings":["Silicon Austria Labs,Linz,Austria","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Austria Labs,Linz,Austria","institution_ids":["https://openalex.org/I4210123126"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022268131","display_name":"Diego Gigena Ivanovich","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Diego Gigena Ivanovich","raw_affiliation_strings":["Silicon Austria Labs,Linz,Austria","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Austria Labs,Linz,Austria","institution_ids":["https://openalex.org/I4210123126"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051822496","display_name":"P. Juli\u00e1n","orcid":"https://orcid.org/0000-0002-6308-4497"},"institutions":[{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Pedro Juli\u00e1n","raw_affiliation_strings":["Silicon Austria Labs,Linz,Austria","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Austria Labs,Linz,Austria","institution_ids":["https://openalex.org/I4210123126"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210123126"],"apc_list":null,"apc_paid":null,"fwci":0.5409,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52079148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.8677939176559448},{"id":"https://openalex.org/keywords/testbed","display_name":"Testbed","score":0.8103944063186646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6936146020889282},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.6427726149559021},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5331629514694214},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4939189553260803},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4913005232810974},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4868263602256775},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4779401123523712},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4659154713153839},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.45981699228286743},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43816742300987244},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4253385663032532},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3490515351295471},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3459849953651428},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3204704523086548},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2037830352783203},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14185857772827148},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07515674829483032}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.8677939176559448},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.8103944063186646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6936146020889282},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.6427726149559021},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5331629514694214},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4939189553260803},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4913005232810974},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4868263602256775},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4779401123523712},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4659154713153839},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.45981699228286743},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43816742300987244},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4253385663032532},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3490515351295471},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3459849953651428},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3204704523086548},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2037830352783203},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14185857772827148},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07515674829483032},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas46773.2023.10182079","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10182079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323402","display_name":"Universidad Nacional del Sur","ror":"https://ror.org/028crwz56"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1995638662","https://openalex.org/W2067523571","https://openalex.org/W2102310801","https://openalex.org/W2135252045","https://openalex.org/W2289252105","https://openalex.org/W2594492285","https://openalex.org/W2794326156","https://openalex.org/W2887936511","https://openalex.org/W2963893493","https://openalex.org/W3125157485","https://openalex.org/W3158521343","https://openalex.org/W3197898233","https://openalex.org/W4297775537","https://openalex.org/W6737664043"],"related_works":["https://openalex.org/W2986579802","https://openalex.org/W3108691306","https://openalex.org/W4389237622","https://openalex.org/W2166309310","https://openalex.org/W4385753159","https://openalex.org/W4387251107","https://openalex.org/W4214914769","https://openalex.org/W2883256816","https://openalex.org/W4200152843","https://openalex.org/W3033201189"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,7,29,35,48,60,73,95,130],"first":[4,57],"prototype":[5],"of":[6,38,46,65,112,132],"testbed":[8],"System":[9],"on":[10],"chip":[11],"(SoC)":[12],"to":[13,79,100,119,125,137],"design":[14],"and":[15,33,52,123],"evaluate":[16],"different":[17],"Neuromorphic":[18],"Deep":[19],"Neural":[20],"Networks":[21],"(NN)":[22],"cores.":[23],"The$1.25mm\\times":[24],"1.25mm$SoC":[25],"was":[26],"fabricated":[27],"in":[28],"65nm":[30],"CMOS":[31],"technology":[32,121],"implements":[34],"system":[36],"composed":[37],"an":[39,109],"ARM":[40],"based":[41],"microprocessor,":[42],"two":[43,53],"memory":[44],"banks":[45],"32KB,":[47],"QSPI":[49],"serial":[50],"interface":[51],"NN":[54],"accelerators.":[55],"The":[56,92],"one":[58],"is":[59,94,115],"novel":[61],"neuromorphic":[62],"accelerator":[63],"consisting":[64],"a$5\\times":[66],"5$kernel":[67],"Symmetrical":[68],"Simplicial":[69],"(SymSimp)":[70],"core":[71],"with":[72,135],"depthwise":[74],"separable":[75],"structure,":[76],"which":[77,114],"allows":[78],"efficiently":[80],"implement":[81,101],"multi-channel":[82],"convolutional":[83],"layers":[84],"by":[85],"breaking":[86],"3D":[87],"kernels":[88],"into":[89],"2D":[90],"kernels.":[91],"second":[93],"3\u00d73":[96],"conventional":[97],"MAC":[98],"engine":[99],"the":[102,126],"fully":[103],"connected":[104],"layers.":[105],"Experimental":[106],"results":[107],"show":[108],"energy":[110],"efficiency":[111],"0.49pJ/OP,":[113],"competitive":[116],"when":[117],"compared":[118],"similar":[120],"ICs,":[122],"extrapolated":[124],"MobileNetworkV2":[127],"ImageNet":[128],"represents":[129],"factor":[131],"2":[133],"improvement":[134],"respect":[136],"NVIDIA":[138],"Jetson":[139],"Nano.":[140]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}