{"id":"https://openalex.org/W4385080034","doi":"https://doi.org/10.1109/iscas46773.2023.10182052","title":"An Open-Source $4 \\times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow","display_name":"An Open-Source $4 \\times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow","publication_year":2023,"publication_date":"2023-05-21","ids":{"openalex":"https://openalex.org/W4385080034","doi":"https://doi.org/10.1109/iscas46773.2023.10182052"},"language":"en","primary_location":{"id":"doi:10.1109/iscas46773.2023.10182052","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10182052","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100763454","display_name":"Po\u2010Han Chen","orcid":"https://orcid.org/0000-0001-9760-9565"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Po-Han Chen","raw_affiliation_strings":["Stanford University,Electrical Engineering,Stanford,USA","Electrical Engineering, Stanford University, Stanford, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University,Electrical Engineering,Stanford,USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Electrical Engineering, Stanford University, Stanford, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112964886","display_name":"Charles Tsao","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles Tsao","raw_affiliation_strings":["Stanford University,Electrical Engineering,Stanford,USA","Electrical Engineering, Stanford University, Stanford, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University,Electrical Engineering,Stanford,USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Electrical Engineering, Stanford University, Stanford, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029554261","display_name":"Priyanka Raina","orcid":"https://orcid.org/0000-0002-8834-8663"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Priyanka Raina","raw_affiliation_strings":["Stanford University,Electrical Engineering,Stanford,USA","Electrical Engineering, Stanford University, Stanford, USA"],"affiliations":[{"raw_affiliation_string":"Stanford University,Electrical Engineering,Stanford,USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Electrical Engineering, Stanford University, Stanford, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100763454"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.326,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.49921235,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7807749509811401},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.726320743560791},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.658352255821228},{"id":"https://openalex.org/keywords/agile-software-development","display_name":"Agile software development","score":0.6272732019424438},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5801801681518555},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5752557516098022},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5655260682106018},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5018999576568604},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4275967478752136},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42377519607543945},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41001278162002563},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37860649824142456},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18082359433174133},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.14377135038375854}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7807749509811401},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.726320743560791},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.658352255821228},{"id":"https://openalex.org/C14185376","wikidata":"https://www.wikidata.org/wiki/Q30232","display_name":"Agile software development","level":2,"score":0.6272732019424438},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5801801681518555},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5752557516098022},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5655260682106018},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5018999576568604},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4275967478752136},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42377519607543945},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41001278162002563},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37860649824142456},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18082359433174133},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.14377135038375854}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas46773.2023.10182052","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10182052","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320315684","display_name":"Stanford SystemX Alliance","ror":null},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2537959404","https://openalex.org/W2780077279","https://openalex.org/W3123559382","https://openalex.org/W3206404986","https://openalex.org/W4284689293","https://openalex.org/W4286367833","https://openalex.org/W4286571734","https://openalex.org/W4310251122","https://openalex.org/W4327930416","https://openalex.org/W4366371058","https://openalex.org/W6839854492","https://openalex.org/W6846680284"],"related_works":["https://openalex.org/W2388040150","https://openalex.org/W4230718388","https://openalex.org/W2102117846","https://openalex.org/W2002682434","https://openalex.org/W2481546399","https://openalex.org/W3149244010","https://openalex.org/W2047284788","https://openalex.org/W2097141385","https://openalex.org/W2051542972","https://openalex.org/W4245257593"],"abstract_inverted_index":{"With":[0],"the":[1,36,69,75,86,97],"end":[2],"of":[3,100],"Dennard":[4],"scaling,":[5],"hardware":[6,22,102],"specialization":[7],"has":[8],"been":[9],"broadly":[10],"adopted":[11],"in":[12],"computing":[13],"systems":[14],"to":[15,95],"improve":[16],"performance":[17],"and":[18,50,80,91],"energy-efficiency.":[19],"However,":[20],"specialized":[21],"deprecates":[23],"soon":[24],"after":[25],"new":[26],"algorithms":[27],"are":[28],"introduced.":[29],"A":[30],"coarse-grained":[31],"reconfigurable":[32],"array":[33],"(CGRA)":[34],"offers":[35],"programmability":[37],"required":[38],"for":[39],"accommodating":[40],"application":[41],"changes,":[42],"while":[43],"still":[44],"being":[45],"more":[46],"efficient":[47],"than":[48],"FPGAs":[49],"GPUs.":[51],"This":[52,67],"work":[53],"presents":[54],"a":[55],"<tex>$4\\times":[56],"8$</tex>":[57],"CGRA":[58,71,87],"created":[59],"using":[60,74],"an":[61],"open-source":[62,76],"agile":[63,101],"hardware-compiler":[64],"co-design":[65],"framework.":[66,104],"is":[68],"first":[70],"chip":[72],"designed":[73],"SkyWater":[77],"130nm":[78],"technology":[79,98],"OpenRAM":[81],"memory":[82],"compiler.":[83],"We":[84],"present":[85],"architecture,":[88],"implementation":[89],"results,":[90],"silicon":[92],"validation":[93],"results":[94],"verify":[96],"portability":[99],"design":[103]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}