{"id":"https://openalex.org/W4385080069","doi":"https://doi.org/10.1109/iscas46773.2023.10182029","title":"An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time","display_name":"An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time","publication_year":2023,"publication_date":"2023-05-21","ids":{"openalex":"https://openalex.org/W4385080069","doi":"https://doi.org/10.1109/iscas46773.2023.10182029"},"language":"en","primary_location":{"id":"doi:10.1109/iscas46773.2023.10182029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas46773.2023.10182029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029218595","display_name":"Dong-Jick Min","orcid":"https://orcid.org/0000-0002-1208-7671"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Jick Min","raw_affiliation_strings":["School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","institution_ids":["https://openalex.org/I31419693"]},{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102733782","display_name":"Jun\u2010Gi Lee","orcid":"https://orcid.org/0000-0002-3635-5511"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jun-Gi Lee","raw_affiliation_strings":["School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","institution_ids":["https://openalex.org/I31419693"]},{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038055090","display_name":"Kunhee Cho","orcid":"https://orcid.org/0000-0002-3409-0505"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kunhee Cho","raw_affiliation_strings":["School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","institution_ids":["https://openalex.org/I31419693"]},{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059610739","display_name":"Jae Hoon Shim","orcid":"https://orcid.org/0009-0009-4292-4539"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae Hoon Shim","raw_affiliation_strings":["School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University,Daegu,Republic of Korea","institution_ids":["https://openalex.org/I31419693"]},{"raw_affiliation_string":"School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, Republic of Korea","institution_ids":["https://openalex.org/I31419693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.41,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.56206205,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.7066727876663208},{"id":"https://openalex.org/keywords/frequency-compensation","display_name":"Frequency compensation","score":0.6700050830841064},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.6443179845809937},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.556063175201416},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.548701822757721},{"id":"https://openalex.org/keywords/low-dropout-regulator","display_name":"Low-dropout regulator","score":0.5396949648857117},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.5334864854812622},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.45684823393821716},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43093883991241455},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4290424585342407},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.3988327980041504},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.3971714377403259},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3756881356239319},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37501421570777893},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3372231721878052},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2916467487812042},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26826393604278564},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21709689497947693},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.10923472046852112},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10832005739212036}],"concepts":[{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.7066727876663208},{"id":"https://openalex.org/C131782439","wikidata":"https://www.wikidata.org/wiki/Q1455581","display_name":"Frequency compensation","level":4,"score":0.6700050830841064},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.6443179845809937},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.556063175201416},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.548701822757721},{"id":"https://openalex.org/C140501009","wikidata":"https://www.wikidata.org/wiki/Q6692746","display_name":"Low-dropout regulator","level":5,"score":0.5396949648857117},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.5334864854812622},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.45684823393821716},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43093883991241455},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4290424585342407},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.3988327980041504},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.3971714377403259},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3756881356239319},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37501421570777893},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3372231721878052},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2916467487812042},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26826393604278564},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21709689497947693},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.10923472046852112},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10832005739212036},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas46773.2023.10182029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas46773.2023.10182029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"},{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W2009198262","https://openalex.org/W2015674476","https://openalex.org/W2031283182","https://openalex.org/W2034720635","https://openalex.org/W2035713928","https://openalex.org/W2054716548","https://openalex.org/W2088405320","https://openalex.org/W2090683789","https://openalex.org/W2100065836","https://openalex.org/W2111172002","https://openalex.org/W2117965437","https://openalex.org/W2152124352","https://openalex.org/W2156889609","https://openalex.org/W2158426860","https://openalex.org/W2158523304","https://openalex.org/W2217616241","https://openalex.org/W2344336685","https://openalex.org/W2760813205","https://openalex.org/W2894668784","https://openalex.org/W2897351503","https://openalex.org/W2962916455","https://openalex.org/W3010874605","https://openalex.org/W3015876354","https://openalex.org/W3015989642","https://openalex.org/W6632975531"],"related_works":["https://openalex.org/W2149499655","https://openalex.org/W2023543646","https://openalex.org/W2964319857","https://openalex.org/W2131534127","https://openalex.org/W2021344914","https://openalex.org/W3120080380","https://openalex.org/W2164557692","https://openalex.org/W2347548253","https://openalex.org/W2092068860","https://openalex.org/W2089097615"],"abstract_inverted_index":{"A":[0],"typical":[1],"digital":[2],"low-dropout":[3],"regulator":[4],"(DLDO)":[5],"that":[6,27],"is":[7],"clocked":[8],"with":[9,93],"a":[10,25,73,78,83,94],"fixed":[11],"frequency":[12,45],"suffers":[13],"from":[14],"the":[15,43,50,53,88,101],"trade-offs":[16],"between":[17],"power,":[18],"speed,":[19],"and":[20,32,46,82],"stability.":[21],"This":[22],"paper":[23],"proposes":[24],"DLDO":[26],"achieves":[28,77],"both":[29],"fast":[30],"settling":[31,80],"low":[33],"power":[34],"consumption":[35],"without":[36],"limit-cycle":[37],"oscillation":[38],"(LCO)":[39],"by":[40],"adaptively":[41],"changing":[42],"clock":[44,51],"eventually":[47],"turning":[48],"off":[49],"in":[52,72],"steady":[54],"state.":[55],"The":[56,68],"proposed":[57,69],"LDO":[58,70],"also":[59],"features":[60],"an":[61],"inverter-based":[62],"droop-compensation":[63],"circuit":[64],"for":[65,87],"output-capacitor-free":[66],"operation.":[67],"designed":[71],"28-nm":[74],"CMOS":[75],"process":[76],"70-ns":[79],"time":[81],"137-mV":[84],"droop":[85],"voltage":[86],"400-mA":[89],"load":[90],"current":[91],"transition":[92],"2.6-ns":[95],"edge":[96],"time,":[97],"which":[98],"translates":[99],"to":[100],"figure":[102],"of":[103,105],"merit":[104],"4.8":[106],"fs.":[107]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}