{"id":"https://openalex.org/W4385079953","doi":"https://doi.org/10.1109/iscas46773.2023.10181992","title":"A 12T SRAM in-Memory Computing differential current architecture for CNN implementations","display_name":"A 12T SRAM in-Memory Computing differential current architecture for CNN implementations","publication_year":2023,"publication_date":"2023-05-21","ids":{"openalex":"https://openalex.org/W4385079953","doi":"https://doi.org/10.1109/iscas46773.2023.10181992"},"language":"en","primary_location":{"id":"doi:10.1109/iscas46773.2023.10181992","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas46773.2023.10181992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072325815","display_name":"Gin\u00e9s Dom\u00e9nech\u2010Asensi","orcid":"https://orcid.org/0000-0002-2419-9275"},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Gines Domenech-Asensi","raw_affiliation_strings":["Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063226771","display_name":"R. Ru\u0131\u0301z","orcid":"https://orcid.org/0000-0002-3890-8124"},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ram\u00f3n Ruiz-Merino","raw_affiliation_strings":["Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038373417","display_name":"Juan Zapata","orcid":"https://orcid.org/0000-0002-7798-3928"},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Zapata-Perez","raw_affiliation_strings":["Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Cartagena,Dpto. de Electrónica, Tecnología de Computadoras y Proyectos,Cartagena,Spain","institution_ids":["https://openalex.org/I3123212020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013362780","display_name":"Jos\u00e9 \u00c1ngel D\u00edaz\u2010Madrid","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100615","display_name":"Centro Universitario de la Defensa en San Javier","ror":"https://ror.org/00nqz4988","country_code":"ES","type":"education","lineage":["https://openalex.org/I4210100615"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 A. D\u00edaz-Madrid","raw_affiliation_strings":["Centro Universitario de la Defensa,Dpto. de Ingeniería y Técnicas Aplicadas,Santiago de la Ribera,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centro Universitario de la Defensa,Dpto. de Ingeniería y Técnicas Aplicadas,Santiago de la Ribera,Spain","institution_ids":["https://openalex.org/I4210100615"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5409,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52064608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7642160654067993},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6608316898345947},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.5786300301551819},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.5711530447006226},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.47542551159858704},{"id":"https://openalex.org/keywords/pixel","display_name":"Pixel","score":0.4723571240901947},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4565010964870453},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42140090465545654},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3542504608631134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3076876401901245},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.2834033966064453},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.26941099762916565},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13704326748847961}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7642160654067993},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6608316898345947},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.5786300301551819},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.5711530447006226},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.47542551159858704},{"id":"https://openalex.org/C160633673","wikidata":"https://www.wikidata.org/wiki/Q355198","display_name":"Pixel","level":2,"score":0.4723571240901947},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4565010964870453},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42140090465545654},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3542504608631134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3076876401901245},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.2834033966064453},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.26941099762916565},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13704326748847961},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas46773.2023.10181992","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas46773.2023.10181992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2591601611","https://openalex.org/W2920326572","https://openalex.org/W2965587479","https://openalex.org/W2969812992","https://openalex.org/W3085521240","https://openalex.org/W3091315548","https://openalex.org/W3200753201","https://openalex.org/W3201362361","https://openalex.org/W4292070340"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W2967161359","https://openalex.org/W3211992815","https://openalex.org/W1976168335","https://openalex.org/W4308090481"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,49,82,129],"current":[4],"mode":[5],"differential":[6],"in-memory":[7],"computing":[8],"architecture":[9,18,104],"to":[10,28,36,62,70],"be":[11],"used":[12],"in":[13,108],"convolutional":[14],"neural":[15],"networks.":[16],"The":[17,44,103,124],"is":[19,46],"based":[20,47],"on":[21,48],"CMOS":[22,83,110],"SRAM":[23],"cells":[24],"with":[25,72],"added":[26],"circuitry":[27],"perform":[29],"the":[30,87,96,99],"multiply":[31],"and":[32,85,114,134,136],"accumulate":[33],"operations":[34],"required":[35],"compute":[37],"convolutions":[38],"of$3\\times":[39],"3$masks":[40],"over$32\\times":[41],"32$pixel":[42],"images.":[43],"convolution":[45],"mixed":[50],"signal":[51],"approach":[52],"where":[53],"analog":[54,64,78],"inputs":[55],"are":[56],"multiplied":[57],"by":[58],"single":[59],"bit":[60],"weights":[61],"obtain":[63],"outputs.":[65],"It":[66],"has":[67,105,117],"been":[68,106,118],"designed":[69],"operate":[71],"an":[73],"input":[74],"data":[75],"stream":[76],"of":[77,90,98,131,138],"values":[79],"coming":[80],"from":[81],"sensor":[84],"allows":[86],"cascaded":[88],"connection":[89],"several":[91],"stages":[92],"as":[93,95],"well":[94],"use":[97],"ReLU":[100],"activation":[101],"operator":[102],"synthesized":[107],"standard":[109],"180":[111],"nm":[112],"technology":[113],"its":[115],"performance":[116],"tested":[119],"through":[120],"device":[121],"level":[122],"simulations.":[123],"whole":[125],"circuit":[126],"operates":[127],"at":[128],"frequency":[130],"10":[132],"MHz":[133],"achieves":[135],"efficiency":[137],"90.9":[139],"TOPS/W":[140]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}