{"id":"https://openalex.org/W4385187236","doi":"https://doi.org/10.1109/iscas46773.2023.10181447","title":"Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect","display_name":"Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect","publication_year":2023,"publication_date":"2023-05-21","ids":{"openalex":"https://openalex.org/W4385187236","doi":"https://doi.org/10.1109/iscas46773.2023.10181447"},"language":"en","primary_location":{"id":"doi:10.1109/iscas46773.2023.10181447","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10181447","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037714507","display_name":"Pratik Shrestha","orcid":"https://orcid.org/0000-0002-7128-0893"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pratik Shrestha","raw_affiliation_strings":["Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059641297","display_name":"Ioannis Savidis","orcid":"https://orcid.org/0000-0003-4230-1795"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ioannis Savidis","raw_affiliation_strings":["Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":2.1635,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.86554933,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mean-absolute-percentage-error","display_name":"Mean absolute percentage error","score":0.8149234056472778},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5514347553253174},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5500518083572388},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5117266178131104},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5008480548858643},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.47195497155189514},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4404986500740051},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.43132662773132324},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.428036093711853},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.41445836424827576},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.28217554092407227},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2628222703933716},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22195863723754883},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.19210946559906006},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.18243756890296936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15882408618927002},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15208783745765686}],"concepts":[{"id":"https://openalex.org/C150217764","wikidata":"https://www.wikidata.org/wiki/Q6803607","display_name":"Mean absolute percentage error","level":3,"score":0.8149234056472778},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5514347553253174},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5500518083572388},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5117266178131104},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5008480548858643},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.47195497155189514},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4404986500740051},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.43132662773132324},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.428036093711853},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.41445836424827576},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.28217554092407227},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2628222703933716},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22195863723754883},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.19210946559906006},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.18243756890296936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15882408618927002},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15208783745765686},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas46773.2023.10181447","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/iscas46773.2023.10181447","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2523246573","https://openalex.org/W2792643794","https://openalex.org/W2794046273","https://openalex.org/W2998169401","https://openalex.org/W3091933103","https://openalex.org/W3109493217","https://openalex.org/W3152893301","https://openalex.org/W3171752851","https://openalex.org/W4241389239","https://openalex.org/W4288419263","https://openalex.org/W4297822251","https://openalex.org/W4297822295","https://openalex.org/W4297822317","https://openalex.org/W4312754249","https://openalex.org/W6727249380","https://openalex.org/W6749029207","https://openalex.org/W6760045743","https://openalex.org/W6843122435","https://openalex.org/W6843334175","https://openalex.org/W6843628672"],"related_works":["https://openalex.org/W2361901082","https://openalex.org/W2167484077","https://openalex.org/W2111591643","https://openalex.org/W3126942597","https://openalex.org/W1977304091","https://openalex.org/W1866752631","https://openalex.org/W1980984060","https://openalex.org/W2118774291","https://openalex.org/W2007278173","https://openalex.org/W2148021977"],"abstract_inverted_index":{"An":[0],"accurate":[1],"early":[2],"estimate":[3],"of":[4,20,48,60,124,141,159,176],"the":[5,15,21,26,43,56,61,81,84,90,103,107,142,149,153,169,172,181],"post":[6,44,57,65],"routing":[7,45],"inter-connect":[8],"parasitics":[9],"allows":[10],"for":[11,80,97,168],"pre-emptive":[12],"changes":[13],"to":[14,41,148],"circuit":[16,50],"in":[17,126,129,161,166],"earlier":[18],"phases":[19],"design":[22,27,73,110],"flow,":[23],"significantly":[24],"reducing":[25],"time":[28],"and":[29,55,131,163],"effort.":[30],"In":[31],"this":[32],"work,":[33],"graph":[34],"based":[35,112],"deep":[36],"regression":[37],"models":[38],"are":[39],"proposed":[40,100,135],"predict":[42],"interconnect":[46,62],"capacitance":[47,67],"a":[49,70,78],"by":[51,69,106,180],"utilizing":[52],"layout":[53],"information":[54],"placement":[58,66],"estimates":[59],"parasitics.":[63],"The":[64,99,134],"determined":[68,179],"commercial":[71,108,150],"physical":[72,109],"tool":[74],"is":[75],"used":[76],"as":[77,146,178],"baseline":[79,104],"models,":[82,119],"with":[83,120,152,171],"mean":[85,91],"absolute":[86,92],"percentage":[87],"error":[88,93],"(MAPE),":[89],"(MAE),":[94],"and$R^{2}$score":[95],"calculated":[96],"comparison.":[98],"methodology":[101,136],"outperforms":[102],"provided":[105],"tools":[111],"on":[113],"results":[114],"obtained":[115],"across":[116],"all":[117],"trained":[118],"an":[121,156],"average":[122,157],"improvement":[123,158],"23.39%":[125],"MAPE,":[127],"5.33%":[128],"MAE,":[130],"1%":[132],"in$R^{2}$score.":[133],"also":[137],"provides":[138],"better":[139],"prediction":[140],"worse":[143],"case":[144],"errors":[145,177],"compared":[147],"tool,":[151],"model":[154],"providing":[155],"47.43%":[160],"MAPE":[162],"14.31":[164],"%":[165,175],"MAE":[167],"nets":[170],"largest":[173],"1":[174],"tool.":[182]},"counts_by_year":[{"year":2024,"cited_by_count":4}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
